搜索资源列表
lcd_test1
- 基于xilinx ISE的microblaze模块完成的流水灯程序，芯片为virtex-5-Program of water-led which is based on xilinx ISE microblaze.The cell is virtex-5.
shuzizhong
- 我做的是基于fpga的一个数字钟的设计用的是xilinx ise开发环境-What I do is design a digital clock based fpga xilinx ise with the development environment
uart
- 利用xilinx 公司的ise软件基于verilog HDL实现UART控制程序-based on the xilinx ise and use verilog HDL language to achieve the purposes that control the uart.
testbench
- 这是基于xilinx ise软件中pci核的仿真程序。文件包括激励程序，顶层程序。可以用于modelsim仿真-This is based on xilinx ise software pci core simulation program. Files include incentive program, the top program. It can be used to simulate modelsim
uart2
- 基于Xilinx ISE的uart传输代码，使用verilog语言完成-Based on Xilinx ISE uart transmission code, completed with verilog language.
3-example_dt_2
- Vhdl编写的数码管驱动，动态7段码，FPGA实验板，Xilinx ISE实验环境-Vhdl write digital tube drive, dynamic 7-segment code, FPGA experimental board, Xilinx ISE experimental environment
1-example_led_4
- Verilog编写的计数闪灯，FPGA实验板，Xilinx ISE实验环境-Verilog prepared by flash count, FPGA experimental board, Xilinx ISE experimental environment
1-example_led_5
- Verilog编写的移位闪灯（跑马灯），FPGA实验板，Xilinx ISE实验环境-Verilog prepared by a shift flash (marquees), FPGA experimental board, Xilinx ISE experimental environment
VHDL-projects
- I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
fpga_counter_Verilog
- 此文件是基于xilinx ise平台上开发的计数器，产生可调的脉冲，也可进行分频。-This document is based on xilinx ise platform counter, adjustable pulse generation, but also for the division.
Counter3
- 基于Xilinx 的ISE 14.7 的计数器程序，包含testbench文件和约束文件-Based on the Xilinx ISE 14.7 Counter program, including testbench and constraints files
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
xilinx_ISE-iMPACT
- Xilinx ise环境下进行impact，下载写好的程序-Conduct impact, download programs written under Xilinx ise environment
IP_COE_Abs2Rel
- 编程辅助软件，将Xilinx ISE 14.x IP核含有的COE文件从绝对路径改成相对路径-Progrmming assisting software, Xilinx ISE 14.x IP core have COE file absolute path change into relative path
Test_Avnet
- A demo for a avnet spartan 3a board in Xilinx ISE Design Suite.
chuanxing
- VHDL的串行通信程序,硬件描述语言，使用xilinx ISE软件-VHDL serial communication program
singleTcpu
- 单周期cpu设计，基于xilinx ISE环境设计，使用MIPS语言-Single cycle, the CPU is designed, based on xilinx ISE environment design, the use of MIPS language
license
- Xilinx ISE13.1破解器，能够对XilinxISE13.1软件进行破解-Xilinx ISE 13.1 software cracker, generate license files, ISE13.1 crack
verilog-ethernet-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
verilog-image-decompressor-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.