搜索资源列表
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
cpld_ads7844_50M(9-24)
- 用ads7844采集数据,用cpld做时序控制,通过串口观察和记录采集结果,用verilog编写,通过开发板验证-Collected data using ads7844 timing control with cpld verilog prepared by the serial observe and record collection results through the development board verification
uartverilog
- 基于fpga的verilog写的uart串口通信实验-Based fpga the verilog write uart serial communication experiment
verilog_uart
- verilog实现串口的调试,用串口调试助手验证通过。-verilog serial debugging and validation by serial debugging assistant.
uart
- 用Verilog HDL编写的串口输入输出程序,可实现数据的传输,在DE2-70上测试通过,有很大的参考价值。-Prepared by the serial input and output using Verilog HDL program can achieve data transmission test by DE2-70, there is a great reference value.
shixian_of_UART
- 串口控制器的FPGA实现,用Verilog语言编写!-Serial controller FPGA, Verilog language!
uart
- veilog 实现FPGA的串口收发器,自发自收,稍作修改可以用于单独发送和接收模块。-verilog describe uart
uart
- 串口通信控制器的Verilog实现。包含4个模块:顶层模块、波特率发生器模块、发送模块和接收模块-The serial communication controller Verilog. Contains four modules: the top-level module, the baud rate generator module, transmitting module and receiver module
ad9850
- 介绍了用FPGA控制DDS产生任意频率范围之内的可调制正弦波,13位BPSK,ASK等。控制字由串口写入。-verilog control AD9850 to get psk ask
MUX_8
- 用verilog实现串口通信程序,通过仿真验证-Serial communication program, is verified by simulation with verilog
UART
- 用verilog实现串口通信程序,通过仿真验证-Serial communication program, is verified by simulation with verilog
ex4
- 串口通讯 可选波特率 verilog 源代码-Selectable baud serial communication verilog source code
UART_TXD_RXD_Verilog
- 开发异步串口FPGA逻辑的说明文档及代码,其中代码用Verilog编写,我就是看这些文档和源码编写了自己的串口程序-uart,txd,rxd ,select baud
uart
- Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明,已接受到一个字节 output [7:0] rx_
serial-communication-source-code
- 这是一个有关于串口通信的原码,主要是用verilog语言来实现,采用的是模块联合方法。-This is a serial communication source code, verilog language, using the module combination method.
rs232
- verilog HDL FPGA串口接受与传输,用于其他电子设备与FPGA之间通过串口进行数据传输-the verilog HDL FPGA serial port receive and transmission, data transmission through the serial port for other electronic equipment and FPGA
UART
- verilog语言编写在CPLD上构建一个遵循串口通信规范的程序-verilog language serial procedures
FPGA-Uart
- fpga串口通讯程序。用Verilog语言编写-fpga serial communication program. Verilog
UART-DISPLAY
- lcd 显示,Verilog语言,串口接收数据,并在LCD中显示,波特率9600,包括主文件,LCD控制文件,波特率发生文件-lcd display Verilog language, serial port to receive data, and the LCD display, baud rate of 9600, including the master file, the LCD control file, the baud rate generator file
rs232
- 用verilog hdl实现RS232串口通讯-RS232 serial communication with the verilog hdl