搜索资源列表
multi8x8
- 该源码为8位乘法器的VHDL语言描述，由一个8位右移寄存器，2个4位加法器例化成8位加法器，一个16位数据锁存器构成。采用移位相加的方式，从被乘数的低位开始，与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit add
add_tree
- 本程序为加法树乘法器，计算16位读写地址，应用于LCD CSTN驱动芯片设计的SRAM的读写控制-This procedure for the adder tree multiplier, calculated 16-bit read and write address, used in LCD CSTN driver IC designed to control the SRAM s read and write
fadd16
- 实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 -Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.
leijiaqi
- 16位流水线加法累加器，用VHDL语言实现，编译仿真通过。-16-bit pipelined adder accumulator, using VHDL language, compiled simulation through.
brentkung_16
- 16位的brentkung加法器树，在xilinx软件下-16-bit brentkung adder tree, under the xilinx software
16bit-CLA
- a 16 bit carry look ahead adder verilog code
adder4-7seg
- 这段程序主要是实现了两个16进制的数据相加减，主要思想是由32位的进位加法器的来。目标板是spartan 3的实验板。-This program is to achieve a two-phase addition and subtraction of data 16 hex, the main idea is to carry the 32-bit adder to. Target board is spartan 3 development board.
lab
- verilog语言设计同步加法器，异步减法器，16位计数器-adder verilog language design synchronous, asynchronous subtractor, 16-bit counter
complement_adder
- 十六位补码加法器，输入为两个16位补码，输出和为17位补码，不虚溢出标志。-Sixteen complement adder, the input to complement the two 16-bit, output, and for the 17 complement, not virtual overflow flag.
verilogfile
- 16位加法器，4位1组的超前进位加法器单独作为1个模块。-16-bit adder.
add32
- 16位DSPTMS320F2407实现32位加法源程序-16 DSPTMS320F2407 source 32-bit adder
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
add16
- designing of 16 bit adder using 4 bit adder using verilog code
adder16
- 16位全加器，适合初学者用，上实验课使用杠杠的-The experimental class of 16-bit full adder, suitable for beginners, on the use of a lever! ! !
adder.ripple
- an 16 bit ripple carry adder
num-seven
- 16位加法器，采用行为描述的建模方式进行建模的加法器-16 bit adder
counter2b
- 基于vhdl完成4位计数器功能的实现，并基于此程序完成16位加法器程序的编写，内附testbench,测试成功。-Based on the vhdl completed four counter function to achieve, and the completion of a 16-bit adder program written based on this program, enclosing testbench, the test is successful.
csa_16
- The folder contains the carry adder code in vhdl. 16 bit adder is designed and coded in vhdl-The folder contains the carry adder code in vhdl. 16 bit adder is designed and coded in vhdl
16位超前进位加法器
- 16位超前进位加法器的报告，报告里面含有主代码测试代码仿真结果(16 bit forward adder)
csa_codes
- carry_select_adder for 16-bit in verilog