搜索资源列表
u26a_spice
- ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
xapp935
- ddr2 controller, verilog source code from xilinx
ddr_ddr2_sdram.rar
- 基于NIOS II的ddr2控制器,配有详细的文档,经验证后可使用.,NIOS II based on the DDR2 controller, equipped with detailed documentation, the experience can be used after certification.
DDR2 SDRAM 控制器的FPGA实现
- DDR2 SDRAM 控制器的FPGA实现,DDR2 SDRAM controller FPGA to achieve
DDR2_Memory_Test
- DDR2 controller which contains verilog files，pdf and so on
DDR2Controller
- DDR2 Controller DDR2 Controller
Intel-IOP341-DDR2-memory-controller-initializtion.
- 可以基于本流程了解IOP Raid处理器在启动时对DDR2内存控制器的初始化。也可以以此了解其他片上系统的DDR2控制器的启动方法。-Understanding of this process can be based on IOP Raid processor at boot time on the DDR2 memory controller initialization. Can also be used to understand the other system-on-chip DDR
ddr2
- 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
AMBA
- 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
Xil3SD1800A_MIG
- 基于xc3sd1800afg676的开发板的DDR2的控制器的IPCORE，提供完整的代码和UCF。系统时钟频率为125Mhz。-The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
DDR2_controller
- DDR2控制器IP的设计与FPGA实现，使用verilog语言-DDR2 Controller IP Design and FPGA implementation, use the verilog language
ddr2_test
- 一个用Verilog写的DDR2的控制器（我们项目是在Altera的FPGA）成功仿真，并且使用到了项目中控制DDR2-A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project
The-Speedy-DDR2-Controller-
- The Speedy DDR2 Controller For FPGAs ERSA 2009 Final
ddr2
- leon3系统中ddr2控制器的相关代码（还包包括存储器的仿真模型），该控制器可以与amba2.0的ahb总线相连，机构比较复杂，代码量很大-ddr2 controller code (package includes the memory of the simulation model) leon3 system, the controller can with amba2.0 the ahb bus connected to more complex institutions, the am
ddr2
- 基于xilinx spartan -3A DSP的ddr2控制器-Based on the Xilinx Spartan-3A DSP DDR2 controller
DDR2-verilog
- ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the
t2_hpc
- DDR2的控制器设计，完成功能的验证，以及仿真测试，(DDR2 controller design, complete function verification, and simulation test,)
DDR2_Control
- 本人用verilog编写的DDR2控制器，经测试可用。(I am prepared to use verilog DDR2 controller, the test is available.)