搜索资源列表
Wireless_Communication_FPGA_Design
- 通信经典书籍《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，学通信的人有福了-Wireless_Communication_FPGA_Design
F7-2VT-1DR
- 2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
ram
- 用FPGA做的RAM，源码，调试通过，有工程-FPGA to do with RAM, source code, debugging through, there are works
fifo
- 用FPGA做的fifo，源码，调试通过，有工程和波形文件-FPGA to do with the fifo, source code, debugging through, there are engineering and waveform file
61EDA_B282
- fpga核心源码，有利于学习，适合初学者学习-fpga core source code, there is conducive to learning, suitable for beginners to learn
decorder
- FPGA驱动LED静态显示,VHDL实现的源码-FPGA-driven LED static display, VHDL source code to achieve
fre500000
- 等精度数字频率计的Verilog源码，从上到下的设计思路，分为6个模块。上过Altera公司的FPGA板。 供大家参考，希望大家不要照抄！-Such as precision digital frequency meter Verilog source code, from top to bottom of design ideas, divided into six modules. Been to Altera' s FPGA boards. For your reference, h
FPGADDSVHDL
- 基于FPGA的DDS源码，可用，简单易懂-FPGA-based DDS source code, available, easy to understand
FPGA_Book_cd
- 《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，本书内容还是非常丰富的，涉及无线通信领域各个方面。不过对于一些比较新的技术，其FPGA实现部分过于简略，难以在工程中实用化。-" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of
CAN_I2C_USB_yuanma
- CAN总线，I2C，USB等的FPGA实现源码，可以利用原有代码，快速开发出自己的代码，物有所值-CAN bus, I2C, USB, etc. FPGA implementation source code, we can use the original code, and to quickly develop its own code, value for money
clock
- 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
traffic_light
- 基于VHDL的FPGA交通灯设计源码，可以实现交通灯信号变化的控制-VHDL for FPGA-based design of traffic light source, can achieve the control of traffic light signal change
48_fir_4_tb
- fpga控制lcd1602的v-log源码-fpga control lcd1602 the v-log Source
48_fir_tb_1
- fpga控制lcd1602的v-log源码-fpga control lcd1602 the v-log Source
cycloneIII_3c120_dev_niosII_standard
- 该源码是关于FPGA片上系统sopc的nios处理器设计，他实现了led，lcd以及Internet网络各种功能，源码已经测试通过，读者可以使用-The source is on the FPGA chip on the system sopc the nios processor design, he realized the led, lcd, and Internet networking features, source code has been tested, the reader
FPGA_DDS
- 基于FPGA的DDS信号发生器产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-FPGA-based VHDL source DDS signal generator and the test stimulus file matlab model simulation in modelsim adopted under
testbench
- 介绍了fpga设计中，利用testbench设计源码测试激励文件，很方便很详细-Introduced fpga design, test stimulus using testbench design source files, it is more convenient
VHDLseven-segmentdecoder
- VHDL在液晶显示上的七段译码器源码,应用于FPGA,ASIC等硬件设计-VHDL in the seven-segment liquid crystal display on the decoder source code, used in FPGA, ASIC and other hardware design
VGA2
- 基于FPGA的VGA显示程序 测试过的，是VHDL源码-FPGA-based VGA display program tested, is VHDL source
O_DDS_PHASE
- 包括了DDS设计的全部源码，其中相位和频率均可调，可直接应用于sopc/fpga设计中-DDS design includes all the source code, which can be adjusted for phase and frequency can be directly applied to sopc/fpga design