搜索资源列表
HDMI_FPGA
- 该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植-The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted
FPGA_Vision
- 该源码为基于FPGA的工业现场实时监控界面的设计，本模块可实际运用于FPGA工业应用场合，也可以作为FPGA设计的参考-The source code for the FPGA-based industrial real-time monitoring interface design, the module can be used in the actual application of FPGA industry applications, can also be used as a ref
FPGA_txt
- 该源码为基于FPGA所开发的TXT文本阅读器，本模块可运用于阅读器开发的实际运用中，并且可用作FPGA开发各类阅读器的模板框架-The source code for the development of FPGA-based TXT text reader, the module can be used in the practical development of the reader, and can be used as FPGA development of various types
verilog
- 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyc
vhdl
- 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0用VHDL编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 prepared using VHDL, t
ethernet_verilog
- 1000M以太网UDP协议在FPGA的实现源码，测试通过-1000M Ethernet UDP protocol in the FPGA to achieve source, the test passed
DDR2_Control
- 本源码是用FPGA控制DDR2芯片的vhdl源码，并使用了modelsim仿真软件测试代码-The source is the use of FPGA control DDR2 chip vhdl source, and the use of modelsim simulation software test code
SKILLED-6133Ebook-8773832FPGA--3779
- 此源码的SKILLED-6133Ebook-8773832FPGA 3779的功能还是比较强大的，同学们可以学习用-The source of fpga ebook SKILLED- 6133-6133-3779 or more powerful, the students can learn to use
SHORT_TRAINING
- 基于XILINX FPGA的OFDM通信系统基带设计之短训练序列模块源码-Baseband OFDM communication system design based on XILINX FPGA module source of short training sequence
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
seg7_verilog
- 七段式LED数码管驱动，Verilog源码，FPGA开发学习。硬件描述语言基础学习。-LED driver
uartfifo
- 串口通信例程，使用FIFO数据缓存。Verilog源码，基于FPGA的uart开发，加深理解。-uart communication
verilogiic1121
- IIC通信Verilog源码，基于FPGA的IIC时序，有助提高对串行通信的认识。-IIC communication
XilinxPFPGAKaiFaShiYongJiaoCheng
- 《Xilinx FPGA开发实用教程（第2版）》所附源码-XILINX FPGA
chengfaqi
- 经过改良的乘法器，硬件实现，FPGA，verilog源码-Improved multiplier, hardware implementation, FPGA, Verilog source code
myCpu2
- CPU硬件实现，能运行基本程序，FPGA，verilog源码-CPU hardware implementation, can run the basic procedures, FPGA, Verilog source code
Watch
- FPGA开发板的简易时钟源码，开发环境为vivado-FPGA development board of the simple clock source, the development environment for vivado
至简设计法--特效呼吸灯
- 特效呼吸灯 工程说明 本模块的功能要求是，实现8个灯前1s慢慢变暗，后1s慢慢变亮，不断重复以上操作。 案例补充说明 呼吸灯效果的LED每时每刻都在以不同的功率工作，以不同的亮度值拟合亮度变化，从而形成非常平顺柔和的灯光特效。亮度变化实际上是通过占空比的变化周期来确定的。占空比通过cnt2的计数来变换，而每次变化为1ms，因此PWM的周期是1ms。(Special effects breathing lamp Engineering descr iption The functional r
8b10b
- ALERA fpga 8B10B转换源码，用于实现8B转10B，10B转8B功能。(ALTERA fpga 8B10B conversion source, used to achieve 8B to 10B, 10B to 8B function)
bingo_spi_test
- 利用SPI实现FPGA和外设之间的通信。经过Modelsim仿真验证。（为FPGA设计技巧与案例开发详解一书源码）(Using SPI to implement communication between FPGA and peripheral. After Modelsim simulation verification. (for FPGA design techniques and case development detailed explanation of a book source