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148个verilog hdl小程序（有很多testbench）——
- 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
testbench模版
- testbench测试模版
比较器的测试矢量
- 一个很好的testbench的例子。
8051单片机源码verilog版本
- 8051单片机源码verilog版本 包括rtl， testbench， synthesis ,Verilog source code version of 8051, including rtl, testbench, synthesis
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
rom_des
- DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
testbench
- how to write testbench,use vhdl-how to write testbench, use vhdl
testbench
- 利用system verilog写仿真测试程序，详细介绍system verilog的语法，及教程 -use system verilog write testbench
testbench
- 这是讲述如何编写testbench的，我认为很经典的。值得一看-This is how to prepare Testbench, I think is very classic. Worth a visit
TestBench
- 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_log
uart-vhdl-testbench
- simple uart vhdl behavioural model (package) vhdl testbench example
testbench
- vhdl modelsim testbench examples-vhdl modelsim testbench for modelsim with vhdl examples
testbench
- 详细介绍了在vhdl语言仿真中怎么编写测试平台代码.-introduce how to write testbench in VHDL
testbench
- altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
testbench
- 介绍了fpga设计中，利用testbench设计源码测试激励文件，很方便很详细-Introduced fpga design, test stimulus using testbench design source files, it is more convenient
testbench(vhdl)
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-wrting testbench
writing-testbench
- 教你如何写VHDL或VerilogHDL的testbench文件，非常有利于FPGA的波形仿真-Teaches you how to write VHDL or VerilogHDL the testbench file, is very conducive to the waveform simulation of FPGA
Testbench
- 掌握多顶层结构化Testbench的方法-Testbench to know more structured way to the top
Modsim-AND-testbench
- 关于fpga中，测试平台testbench的技巧，及仿真软件MOSIDISIM-About fpga skills test platform testbench, and simulation software MOSIDISIM