搜索资源列表
async_reset_dff
- 异步复位的D触发器 vhdl fpga xilinx spartan-3e-D flip flop async-reset vhdl fpga xilinx spartan-3e
watch_sc4
- 用VHDL语言设计一个简易秒表，开发工具是xilinx，有重置功能-design a second-counting watch with Language VHDL and platform xilinx
qiangdaqi11
- 用VHDL语言设计一个抢答器系统，能反映抢答者的抢答并作出回应，xilinx平台-design a answer competition system with language VHDL and platform Xilinx
2012-05-27-ADC-Light-Sensor-Avago-APDS-9005-020.z
- ADC Light Sensor Avago APDS-9005-020 VHDL solution running on a Xilinx Spartan 6: Reading out light intensity from an Avago APDS-9005-020 using an average DAC and two additional digital control lines.
EDA--light-water-
- 用VHDL设计的流水灯，基于xilinx ise-vhdl light water
3des_vhdl
- 3DES算法VHDL实现，适用于XILINX FPGA-3DES algorithm VHDL Implementation，fit to XILINX FPGA
8051_latest
- this project is regarding 8051 microcontroller development in VHDL language using xilinx tool for synthesis of code-this project is regarding 8051 microcontroller development in VHDL language using xilinx tool for synthesis of code
I2C_ise7_bak
- Uncomment the following library declaration if instantiating any Xilinx primitives in this code. library UNISIM use UNISIM.VComponents.all I2C DRIVE IN VHDL
11_170_1
- Xilinx的FPGA的PCIe的VHDL代码，已经验证。-Xilinx FPGA Virtex-5 PCie
DACtest
- Spartan 3E - DAC- VHDL. It is a vhdl code for Xilinx Spartan 3E fpga to run ADC and AMP on the board via SPI interface.
code_lab5_num1
- Xilinx 的VHDL设计时钟 -VHDL design clock clock the Xilinx Xilinx VHDL design
dac_adc
- vhdl dac_adc.mdl its sysgen model file for xilinx platform
Bssppartan3a
- 一种基于xilinx公司的FPGA开发板spartan3的一个用键盘控制制vga输出的vhdl源代码程序源码，能实现高清晰的视频输出. -Based xilinx company FPGA development board spartan3 of a keyboard control system vga output vhdl source code program source code, can achieve high-definition video output.
Encoder_3
- A simple encoder schematic, described in VHDL and tested on a Spartan 3A Starter Kit board by Xilinx
VHDL_60-system_counter
- 用VHDL语言编写的简易60进制的可调节计数器，用于Xilinx ISE软件-A 60-digit system settable countr using VHDL, programming using Xilinx ISE
spar6
- pcie xilinx 接口文件,vhdl语言编写-pcie xilinx interface file,writen with vhdl
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
vga_core
- Code VHDL for control VGA FPGA: Xilinx, Altera
chuot
- code VHDL/ Verilog for Mouser using FPGA: Xilinx, Altera
assigment3
- Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the Mod