搜索资源列表
[FPGA] RAM数据读取-VGA显示
- 依托Xilinx平台,开发的数据读取显示程序,爱好者可以将该段程序嵌入到系统平台中,用于对采集到的数据进行显示。此外,通过添加接口模块,可以实现附带功能
xilinx-tcl
- Xilinx脚本约束手册,从官方直接拿到的,对Xilinx FPGA开发很有用的。-Xilinx tcl handbook, directly got Xilinx。
FPGA-design-and-verification-using-Simulink
- Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ability to functionally simulate a design and use
FPGA-FIR
- 基于Xilinx FPGA实现的系数可装载数字滤波器源代码
xintf-fpga
- 本程序主要是实现xinlinx fpga与dsp之间的双工通信-This program is to achieve duplex communication between xilinx fpga and dsp
FPGA
- 韩福柱老师FPGA实验源码,用vhdl语言在xilinx FPGA上实现,包括ad采集,温度传感器读取,秒表,跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and key
三速以太网代码(FPGA)
- 本代码是运用xilinx的fpga实现千兆网的,同时支持百兆以太网和10兆以太网。内含仿真文件
xilinx-FPGA
- XILINX入门教程,可以帮助初学者熟悉FPGA的基本操作流程-Xilinx starter tutorial, can help beginners to familiarize themselves with the basic operating process of FPGA
FPGA设计高级篇(Xilinx版)
- FPGA设计的高级篇,xilinx出品,适合已经入门想要进阶的学习(FPGA design advanced article, Xilinx produced, suitable for already started, want advanced learning)
szmb
- 用VHDL语言基于ISE,在XILINX FPGA开发板上编写的数字秒表程序(Using VHDL language, based on ISE, in the XILINX FPGA development board prepared by the digital stopwatch program)
uart_2_led_ego1
- 通过uart接受到一个8位的数据,在fpga ego上面用led显示出来(Receive a 8 bit data through UART and display it on FPGA ego with LED)
华为_FPGA设计高级技巧Xilinx篇
- 华为FPGA设计高级技巧Xilinx篇 华为FPGA设计 verilog语言(HuaWei FPGA Advanced design techniques Xilinx)
编译xilinx 库步骤
- 关于编译xilinx 软件库的详细步骤,很有帮助。(Compile the steps for the Xilinx Library)
FPGA分频
- xilinx spant6 PLL分频,生成4个不同频率的时钟,实现LED闪烁。(xilinx spant6 PLL frequency division)
MAKEAMIF
- 用于生成xilinx开发环境中存储器ip core的mif数据文件的程序代码。(this program is used to generate mif file used by xilinx memory ip core.)
MAKEXCOE
- 用于生成xilinx开发环境中存储器ip core的coe数据文件的程序代码。(this program is used to generate coe file used by xilinx memory ip core.)
Half-Adder
- This is an example to implement an Half-adder for xilinx FPGA
ezidebug-code
- Ezidebug 支持Xilinx,chipscope 寄存器链插入、数据采集和导出、重建testbench和软件仿真验证(Ezidebug supports Xilinx, chipscope register chain insertion, data acquisition and export, reconstruction of testbench and software simulation verification)
Embedded-MP3-Player-master
- 利用XILINX FPGA 嵌入式核编写的C语言程序(C language program written in XILINX FPGA embedded core)
ActivePowerMeter(有源功率计)
- 基于Xilinx FPGA的有源功率计,采用的是vertix5平台(Active power meter based on Xilinx FPGA)