搜索资源列表
alu1
- alu,原程序及testbench,供初学者参考-alu, the original procedures and testbench and reference for beginners
vhdl实现alu的源代码
- VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
alu
- ALU modeling verilog codes and testbench
ALU
- VHDL实现ALU的源代码，并且提供了一个详细的testbench-ALU VHDL source code implementation, and provides a detailed testbench
testbenchHw9-Parts-CombCirc
- // Testbench for the following parts found in // MIPS-Parts.V // * 2:1 multiplexer // * 4:1 multiplexer // * Sign extender // * ALU
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
alu_testbench_vhdl_689102300
- ALU的testbench测试，可联合仿真使用-The ALU testbench test can be co-simulation using
pr_step7-(1).vhdl
- 8位alu 附上testbench以供仿真-8 alu attach testbench for simulation
ALU
- 简易的VHDL程序，主要实现ALU的逻辑功能，进行选择和数据的移动。很适合初学者对VHDL的理解。内含有testbench可以进行Qutarus的仿真-Simple VHDL program, the main achievement of the ALU logic functions, to select and move data. VHDL is suitable for beginners to understand. Containing a simulation testbench