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sparc_verilog
- open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
DDS_verilog
- 采用verilog实现了DDS发生器，源码已通过仿真编译已经板级调试，可直接模块化使用。-Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.
counter
- 本文介绍了基于FPGA的数字频率计的设计方法，设计采用硬件描述语言Verilog ，在软件开发平台ISE上完成，可以在较高速时钟频率（48MHz）下正常工作。该数字频率计采用测频的方法，能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware descr iption language Verilog, ISE on t
keyboard
- 用verilog代码编写的交通灯的FPGA工程。可实现南北和东西两条大街的十字路口的交通控制。-Verilog code written with the traffic lights of the FPGA project. Two north-south and east-west can be achieved Street intersection traffic control.
Mult_Frequency
- Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display
lcd11
- verilog 编写的lcd显示程序，结合spartan 3 an开发板，解压即可使用。-verilog written lcd display program, combined with the spartan 3 an development board, decompression can be used.
AD_filter
- AD递推平均滤波算法，采用verilog完成，可直接使用。-AD recursive average filter algorithm, using verilog complete, can be used directly.
ANNA-Y
- 此源程序可包含verilog与vhdl任意倍数的分频，奇数偶数分频均可，均已通过验证，可直接使用。-The source code can contain multiple verilog and vhdl any frequency, both odd and even frequency, are validated and can be used directly.
anna-y0802
- 压缩文件内含有VHDL和VERILOG编写的SDRM控制源码，已通过编译，均可直接使用。-Zip file contains VHDL and VERILOG source code written in SDRM control, has passed the compilation, can be used directly.
f_measure_3
- 示波器源程序，由quartus9.1编写，verilog语言支持。采样频率为1M等效采样速率可以到200M-Oscilloscope source code, written by the quartus9.1, verilog language support. Sampling frequency of 1M to 200M equivalent sampling rate can
77433656timing_bit
- 位同步仿真，有仿真数据的输入，以及转换，可以输入到verilog中仿真-Bit synchronous simulation, simulation data input, and conversion, can be entered into the simulation verilog
weitongbu_datain
- 这是一个很好的仿真位同步，而且记录了输入的数据进行了转化，可以直接用于verilog里面的信号输入仿真-This is a good simulation of bit synchronization, and recorded data were entered into, which can be directly used for signal input verilog simulation
zidongshouhuoji
- 自动售货机的verilog使用，可以作为初学CPLD的一种参考。-Verilog vending machine use, can be used as a reference for beginners CPLD.
uart-
- 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
freqency
- verilog语言 写的 频率计 ，可在1602液晶上显示，代码齐全，经过验证。-verilog language written in the frequency meter can be displayed on the LCD in 1602, code complete, proven.
plj_book
- EDA，verilog 语言写的频率计，一个是测频，一个是产生一定的频率作为信号源，可在cycloneII 上验证，-EDA, verilog language written in frequency counter, one frequency measurement, one is a certain frequency as the signal source can be verified on the cycloneII, thank you! !
11
- 等精度频率计，verilog语言写的，可在开发板上验证，已经试过-And other precision frequency meter, verilog language, and can be verified on the development board, has tried
SRAM
- 进阶实验之SRAM测试，由verilog编写，可直接对sram进行存写-Advanced SRAM test experiments, written by the verilog, can be stored directly on the sram write
rs232
- 这是用verilog语言写的串口自收发实验的源代码，通过板子实验，采用分层模块化设计，代码大家请仔细阅读-It is written in verilog serial transceiver test from the source code through the board experiments, a stratified modular design, code, we can slowly digest
top
- 可实现多路选择,使用的是 verilog，代码清晰易懂-Can achieve multiple choice, using verilog, clear and easy to understand code