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16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
xx_new4
- The purpose of this lab is to introduce the concept of FSMs with a datapath, and to study the usage of more complex test benches. Also, we enforce a rudimentary design methodology by assuming that the students are part of a bigger p
datapath
- MIPS处理器的数据通道VHDL代码，可综合，可仿真，属硬件描述语言，集成电路设计代码
25175bm
- 学生报名管理系统功能简介: /Registration.asp 学生注册系统主文件 报名内容{用户名,密码,确认密码,EMail,QQ号码 ,真实姓名 ,性别,年龄,家庭住址,电话,手机,身份证号码,密码提示问题,安全回答} /user_login.asp 通过注册的帐号：密码：验证码：进行登陆学生 /conn.asp 将此段改成你要的路径DataPath=\"/20070911baoming20/data/#123.mdb\" /admin/login.asp 后台adm
students-manager
- 学生报名管理系统： 报名内容{用户名,密码,确认密码,EMail,QQ号码 ,真实姓名 ,性别,年龄,家庭住址,电话,手机,身份证号码,密码提示问题,安全回答} /user_login.asp 通过注册的帐号：密码：验证码：进行登陆学生 /conn.asp 将此段改成你要的路径DataPath=\"/20070911baoming20/data/#123.mdb\" /admin/login.asp 后台admin admin进行登陆管理,密码是加MD5加密 md5双重加密
25175xshy0912
- 25175 学生会员注册系统 2007 Build 0912 /Registration.ASP 学生注册系统主文件 报名内容{用户名,密码,确认密码,EMail,QQ号码 ,真实姓名 ,性别,年龄,家庭住址,电话,手机,身份证号码,密码提示问题,安全回答} /user_login.asp 通过注册的帐号：密码：验证码：进行登陆学生 /conn.asp 将此段改成你要的路径DataPath=\"/20070911baoming20/data/#123.mdb\" /a
datapath
- for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION-for FPGA IMPLEMENTATION, OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION
ask10
- This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can
DDRSDRAMControllerverilogcode
- 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Fron
Datapaths
- vhdl source code for 8 bit datapath logic
DDR_interface
- 高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 -High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS
BuildingtheCPUdatapath
- Building the CPU datapath
Digital-Computer-Arithmetic-Datapath-Design-Using
- Digital Computer Arithmetic Datapath Design Using Verilog HDL
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
Datapath
- datapath of 8bit synthesized risc processor
datapath
- Open vSwitch switching datapath for Linux.
datapath
- 单片机PIC16C5X的datapath代码，包括ALU,alu_mux,w_reg和各个指令的代码-The datapath PIC16C5X microcontroller code, including ALU, alu_mux, w_reg and each instruction code
datapath
- All writes e.g. Writes to device state (add remove datapath, port, set operations on vports, etc.), Writes to other state (flow table modifications, set miscellaneous datapath parameters, etc.) are protected by ovs_lock.
DataPath
- datapath-datapath of Cpu
DataPath
- Datapath PNG for the Model Sim example.