搜索资源列表
aes_encryption
- aes加密算法的VHDL代码实现，在FPGA芯片上调试过
Algorithms
- 密码算法AES,DES,IDEA,MD5等的基本理论和硬件加速方案，对算法进行fpga硬件加速的优点等
VHDL_AES_ZigBee
- 用VHDL实现的ZigBee模块控制算法以及AES加密算法，用于Xilinx的FPGA!-With the realization of VHDL ZigBee module control algorithm and AES encryption algorithms for Xilinx FPGA!
SSSSS
- 一种实用的基于FPGA的加密算法的设计，有AES和DES-A practical FPGA-based design of encryption algorithm, AES and DES have
1
- 一种基于FPGA的AES算法的低功耗实现,对于AES低功耗设计有帮助作用-FPGA-based AES algorithm to achieve low power consumption, low-power design for the AES helpful
AESFPGA
- 论文介绍了AES算法在FPGA上的实现功能，对AES算法过程进行了优化。-This paper introduces the AES algorithm in FPGA implementation function of the AES algorithm to optimize the process.
fpga_code
- ZLG_EasyFPGA060开发板配套的源程序。包括：AES加密实验及文档，同步FIFO实验等项目。让新手快速掌握FPGA的开发流程，为进一步学习好FPGA打下坚实的基础。-ZLG_EasyFPGA060 development board supporting source. Include: AES encryption and document experiments, synchronous FIFO experiments and other projects. Novice to
des1
- 基于ＦＰＧＡ的ＡＥＳ加密算法的实现 由于其较高的保密级别，AES算法被用来替代DES和3一DES，以适应更为严苛的数据加密需要。-FPGA Implementation of Real-Time Adaptive Image Thresholding
aes_fifo_interface
- aes to fsl with xilinx fpga
aes_fsl_interface
- aes to fsl with xilinx fpga
AES_128
- AES 128 bit with various device interface on FPGA
dec_aes
- decription aes vhdl code for fpga
Project
- 基于FPGA的AES算法的VHDL实现，低内存模式-aes vhdl code
GCM-AES_Implementation_Spec_v2
- AES GCM 算法介绍，对AES算法实现有一定帮助。-This document aims to explore hardware implementation of GCM-AES mode of operation specifically targeting FPGA [1] (Field Programmable Gate Arrays). The aim of such an implementation is to benchmark GCM-AES on FPGA in term
IYUG
- The AES-128 implementation as depicted in Figure 3 has been implemented on the FPGA. This required an initial round key addition followed by ten rounds of S-Box.
20161227_sf
- AES加密算法中的列混合模块的FPGA实现源代码，采用Verillog语言，在软件Quartus II上综合-AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software
avs_aes_latest
- This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA
Coding Files
- We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
AESj 加密解密Verilog
- 128位AES加密解密，可以在FPGA上实现