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Crack_Altera_6[1][1].0-9.1
- quartus版本的破解 从6.1至9.0间所有版本-quartus crack version from 6.1 to 9.0 all versions
I2S
- 用verilog实现的 I2S 源码，可以直接通过Quartus运行-I2S implementation by verilog source code can be run directly through the Quartus ~ ~
Quaturs_Crack_10.0_SP1_Windows
- Quaturs_Crack_10.0_SP1_Windows.rar样方便你下载里面的东西Quartus 10.0 sp1破解下载-Quaturs_Crack_10.0_SP1_Windows.rar like easier for you to download the stuff inside Quartus 10.0 sp1 crack download
WriteDpAddr
- 写DPRAM状态机，Quartus -DPRAM write state machine, Quartus II
ReadDpram
- 读DPRAM状态机，Quartus -DPRAM read state machine, Quartus II
data_extraction
- 可以将matlab生成的dat二进制数据文件，直接生成需要的mif文件，便于在quartus中rom直接调用。-Dat matlab can generate the binary data files directly to generate the mif file, easy to call directly in the quartus in rom.
clk_sync
- 本文件是在ALTERA公司的QUARTUS下VHDL+原理图编写的时钟同步逻辑-This document is in the company' s QUARTUS ALTERA under VHDL+ schematic written clock synchronization logic
exp1.5_mux8_1
- 用VHDL及verylog语言设计一个8选一数据选择器，可以在Quartus II中仿真-Language Design with VHDL and verylog a 8-to-one data selector, you can simulate in the Quartus II
seg7_lut_8_0.rar
- 七段阴极数码管的FPGA控制程序，开发平台为ISE或者quartus,Seven-Segment LED cathode the FPGA control procedures, development platform for the ISE or Quartus
EPM240Prj.rar
- 这是一个verilog HDL 语言的例子，在CPLD器件EPM240上实现了 RS232协议、按键处理、LED数码管显示和每秒加1数码显示。使用quartus ii 7.0 以上打开.,This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plu
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
nios2-flash-override.rar
- 在开发nios2时，当把nios2中写的程序烧录到用epcs4中时会报错，原因是找不到epcs的映射资料，把这个文件，放到quartus根目录的bin文件夹内后，再打开一次flash program，就能下载成功！,Nios2 in the development, when the procedures wrote nios2 writers to use when epcs4 in error, the use of this document, into the root director
DW8051.rar
- 一个兼容keil的8051内核，在Quartus II 8.0 上编译通过的。希望对大家有帮助！！,Keil a 8051-compatible core, the Quartus II 8.0, adopted by the compiler. We want to help! !
flash02
- 一个我自己写的FPGA读写FLASH代码，在QUARTUS 下用verilog编写，falsh的型号是k9f5608u0d,经测试可以用。-I wrote a FLASH FPGA to read and write code, written in QUARTUS next with verilog, falsh model is k9f5608u0d, can be tested.
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
DupalPortRam.rar
- 基于quartus的双端口RAM的完整设计流程，包括建立的工程仿真实现,Quartus-based dual-port RAM of the integrity of the design process, including the establishment of the Engineering Simulation
TaxiPriceCounter.rar
- 数字逻辑实验作品，在maxplus2下开发的出租车计价器系统（Quartus也可运行），实现基本计价功能，可以设置单价（实验报告中友设置方法），内含实验报告，直接打开taxi_price_counter_final.gdf即可运行,Digital logic experiment works, developed in maxplus2 Taximeter system (Quartus can also be run), the realization of the basic pricing
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
EPM240_Uart
- 基于Quartus II的Verilog编写的Uart串口测试程序。数据收发机LED灯测试。-Based on the Verilog Quartus II prepared Uart serial port test program. LED lamp test data transceiver.
mux4
- 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of