搜索资源列表
riscCPU
- 实现 八位RISC cpu 含有V文件和 testbents测试文件(Realization of eight bits RISC cpu)
proghcs1
- 跳码解码程序,样本示例程序,基于risc单片机指令(hopingcode decode sample)
Insiders_Guide_XC166
- The C166S V2 CPU core used in the XC166 seriesmakes extensive use of Reduced Instruction Set Computer (RISC) concepts to achieve its blend of very highperformance at modest cost.
risc_spm_v14
- 使用Altera CycloneIV 用Verilog语言实现一个精简指令集cpu(Using Altera CycloneIV to implement a streamlined instruction set CPU in Verilog language)
MCP_CAN_lib-master
- is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the. ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer.
RISC
- URISC的RTL级设计,Verilog代码(Design: URISC RTL Verilog)
计组project1_riscv-simulator
- 在这个项目中,您将熟悉汇编程序的工作方式以及RISC-V指令集的实现方式。 通过这个项目,您应该学习实现处理器的原理和技术。 您的任务是为小型RISC-V指令集建模汇编器和非流水线处理器。(In this project, you will be familiar with how the assembler work and how the RISC-V instruction set is implemented. Through this project, you should learn
asr_lora_6601-master
- ASR6601 是一款通用的 LPWAN 无线通信 SoC,集成了射频收发器、调制解调器和 32 位 RISC MCU。射频收发器具有 150 MHz 至 960 MHz 的连续频率覆盖范围。调制解调器支持 LPWAN 用例的 LoRa 调制和传统用例的 (G)FSK 调制。调制解调器还支持TX中的BPSK调制以及TX和RX中的(G)MSK调制。LPWAN无线通信模块采用ASR6601设计,可为LPWAN应用提供超远距离和超低功耗通信。 ASR6601可以实现-148 dBm的高灵敏度,最