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uart.rar
- Verilog编写的UART程序源代码。测试成功。支持字符串发送,UART prepared Verilog source code. Successful test. Support string sent
UART
- 这是VHDL编写的UART源码，测试成功，欢饮下载-It is written in UART VHDL source code, the test is successful, Huanyin download
UART
- 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
mini-uart
- Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
UART
- UART通信协议的硬件描述语言代码，用与FPGA的总线接口开发-UART communication protocol of the hardware descr iption language code, using the bus interface with the FPGA development
uart
- this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
URAT_VHDL_CODE
- altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
UART
- 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
UART
- 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
uart
- uart - universal asynchronous receicer and transmitter source code using VHDL
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
uart
- UART串口的VHDL源程序，希望对大家有用-UART serial port of the VHDL source code, we want to be useful
gh_uart_16550_072108
- UART（通用串行收发器）的VHDL源代码，适合硬件工程师在FPGA内部实现多个UART-UART (universal serial transceivers), VHDL source code for hardware engineers in the FPGA to achieve multiple internal UART
Micro_uart
- Micro-uart source code
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
uart-
- 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
uart
- UART vhdl code,recive data from uart port on fpga board
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
UART
- 自己总结的UART的设计及分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the design and analysis of UART, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)