搜索资源列表
s3en_tcp
- 基于spartan3e开发板的嵌入式EDK软件平台下的TCP/IP协议的网口程序-Embedded development board based on spartan3e EDK software platform for TCP/IP protocol network port procedures
2fsk
- 2ASK 模块的Verilog实现，附带完整的测试文件-2ASK Verilog module implementation, with a complete test file
VerilogProjects
- 在quartus II环境下用Verilog实现了8255, 8253, 8259, 8250, DAC0832, ADC0809等微机接口芯片，硬件设计实验课的作品，有些芯片的功能有所简化，但最基本的功能已实现，有完整的时序仿真波形-In quartus II environment achieved with Verilog 8255, 8253, 8259, 8250, DAC0832, ADC0809 and other computer interface chip, hardware
IFFT
- OFDM中的IFFF模块实现，基于verilog实现，通过验证-OFDM module in IFFF
can
- can总线的verilog设计与实现，很好的资料哦-the implention of can bus with verilog
5b6b
- 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输，串行码序列中连续的比特0或比特1的长度不超过5，数据在0和1之间变换的密度很高,并具有直流平衡的特性，有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conver
exer2
- 给定一个频率为33MHz的时钟，试利用该时钟得到一个基本均匀的2.048MHz时钟-Given a frequency of 33MHz clock, try to use the clock to get a basic uniform of the 2.048MHz clock
SERDES
- 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
matrix
- 3x3 matrix implementation in VHDL
QAM16_Demapping
- 用VERILOG写的解16qam程序。本来是针对OFDM设计的，有一定参考价值。-Solutions 16qam with VERILOG written procedures. Was originally designed for OFDM has some reference value.
I2C
- 此源码为基于FPGA的实现I2C总线协议的程序，程序中实现了AT24C02的芯片的读写。-The source code for the FPGA-based implementation of I2C bus protocol of the program, the program is implemented to read and write AT24C02 chip.
TestAD9709_AD9288_Verilog
- 使用Verilog语言控制高速AD9288 Ad9707-Verilog language control using high-speed AD9288 Ad9707
farrow
- 一份很好的数字时延程序（采用farrow算法），采用Verilog HDL，经过测试通过，是我一个雷达项目中的代替模拟时延的。精度很高，并有MATLAB程序验证-A good digital delay, Verilog HDL, procedures, is my test through a radar simulation project instead of the delay. Precision is high, and MATLAB validation
factorial
- verilog code for factorial algorithm
PID
- 用VHDL语言来实现PID算法，文件包含了仿真的所有结果-VHDL language used to implement PID algorithm, the file contains all the simulation results. . .
ENCODE_8B_10B
- 8B-10B编码，Verilog代码，通过编译，仿真，代码规范，清晰-8B-10B code, Verilog code, through the compilation, simulation, code specifications, clear
verilog_testbench_genetator
- 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010---------------
prbs
- 伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
turbo_encoder
- 在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。-Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.
is61lv25616
- 以is61lv25616为例，用verilog实现的SRAM-SRAM implemented verilog