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EXP4_sec
- 秒表 4个7数码管中的任何一个显示任意按键按下的次数。初始值为0,当计数到9时,下一次数值为0。利用Verilog HDL语言,编程实现上述功能。-Stopwatch
verilog2
- 本代码在Quartus II 9.0 (32-Bit)环境编译运行,使用SOPC_NIOSIIFPGA开发板,可作为入门级代码讲解,将50MHZ的频率改为1MHZ,并以此频率为基准计数显示在七段数码管上。(采用verilog语言)-The code in Quartus II 9.0 (32-Bit) environment to run the compiler, the use of SOPC_NIOSIIFPGA development board, entry-level code ca
shuma0-3
- 利用verilog语言编程 以FPGA为开发工具实现数码管0-3显示!-Verilog language programming to the use of FPGA development tools for the realization of digital tube 0-3 show!
decode_display
- 基于FPGA的动态数码管驱动程序,用verilog HDL语言实现。-FPGA-based digital control of dynamic drivers, using verilog HDL language.
calculator
- 课设一个,又臭又长,是一个用verilog编写的计算器,对应革新科技的某个sopc开发平台,键盘会扫描,七段二极管会译码且是并行输出,上传的是整个工程,在该开发平台上基本正常,主程序段编写的较为幼稚,希望大家多多扔玉。注:主程序段预计做八位计算器,后来因为实验平台只有六个数码管无奈之下后两位没接,主程序中的ac有问题,在开发平台上没效果,压缩包里的图是主程序在quartus下的仿真图,开发环境是quartus,不知应选哪项。最后:初次上传欢迎指正 -Set up a class, but als
led7
- 一个用Verilog语言实现的七段数码管显示。包含工程文件和实现文档。-One with the Verilog language implementation of the seven-segment LED display. And the achievement of the document contains the project file.
paobiao
- 基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙,秒,分。 有开始,暂停,复位功能。 学习VerilogHDL的经典例子,添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
user_logic_SEG7_LUT_8
- freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
verilog_seg7
- 买的Altra公司的一款Max II EPM1270T144的电路板,其中的一个用Verilog HDL 编写的驱动数码管的程序,完全可用。-Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.
S9_keyboard
- 基于verilog语言的按键扫描和数码管显示-press scan and LED display
clock
- 这个程序是用verilog hdl语言编写,实现在数码管上显示时间,暂不支持调整-This program is written in verilog hdl to achieve in the digital tube display time, withhold support to the adjustment
timer_set
- 这个是我自己编写的verilog代码,实现的功能是,在数码管上显示时间,按一个键,显示日期,长按一个键,显示秒表。。。时间日期可调-This is my own code written in verilog to realize the function of the digital tube display time, press a button, display the date, long press of a button, display Stopwatch. . . Time a
4computer
- verilog编写的4位计算器带数码管现实和-verilog-4bit computer
LED
- 实现数码管的秒。分钟位显示。时钟1s调一次,下载到板子,通过验证了的verilog程序-To achieve digital control of the second. Minute digital display. 1s adjusted clock time, downloaded to the board, through the verilog program verified
scan
- 用verilog实现数码管扫描的功能,本人已经用Quarter9.0运行成功。-Verilog implementation of digital control with the functions of scanning, I have run successfully with Quarter9.0.
11
- 利用verilog HDL实现在FPGA上的带小数点的数码管显示-Using verilog HDL to achieve in the FPGA on the digital display with decimal point
FPGA_Interface_Equipment
- 跑马灯、串口、矩阵键盘、蜂鸣器、I2C、数码管、拨码开关 vhdl verilog源代码(精华)-Marquees, serial port, matrix keypad, buzzer, I2C, digital control, DIP switch vhdl verilog source code (extract)
seg7_deo1
- 七位数码管显示器,有源程序,编译仿真程序,verilog语言-7 digital tube displays, there is source code, compiled simulation program, verilog language
seg
- 用verilog语言实现数码管控制工作,有问题可以qq咨询,516998649-use the verilog language to drive the seg
baweishumaguan
- 利用Verilog hdl语言编写的8位数码管程序,这对于那些刚学Verilog hdl语言的学习者来说,是不错的入门程序,特别程序里头的分频程序模块,谢谢支持。-Using Verilog hdl language of the eight digital control procedures, which for those just learning Verilog hdl language learners, is a good entry procedures, especially