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一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据,A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data
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基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
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FPGA设计中涉及到的速度与面积互换技巧，本工程的代码用Verilog编写，实现功能串行输入并行输出-It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output
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主要用来实现数据串并转换功能，内附2种实现程序-serial to parallel converter verilog code
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这是I2S总线接口的Verilog实现源代码，包含了计数、左右通道选择、串行转并行等功能。-This is a Verilog I2S bus interface source code, including the count, about channel selection, serial to parallel functions.
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FPGA部分基础功能源代码，适合初学者进行学习仿真，代码可读性强，通俗易懂，逻辑清晰。包括触发器，全加器，分频，并串转换，计数器，序列发生器等Verilog语言源代码。-
Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ
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