搜索资源列表
vivado.2015.4.1.win64
- Vivado 2015.4 破解+License-Vivado 2015.4 Crack and License
vivado-boards-master
- xilinx 的vivado开发板的板级支持包。直接拷贝到vivado安装目录下就可以。-xilinx vivado examples
vivado_init
- 该程序是为vivado初始化和配置，并且还包含有相应的说明文档，是初学xilinx vivado的很好的教程，本例程基于zynq系列的MIZ701N处理器进行开发(The program is vivado initialization and configuration, and also contains the corresponding documentation, is a good beginner Xilinx vivado tutorial, this routine based
digital_clock
- vivado 学习资料 数字时钟设计 新建工程后导入相关文件（source）(digital clock Vivado learning materials Digital clock design, new construction, import related documents (source))
lab2
- Verilog lab2 is used for learning vivado
lab4
- Verilog lab4 is used for learning vivado
lab5
- Verilog lab5 is used for learning vivado
LSFR
- 线性反馈移位寄存器通常用于实现数据压缩电路中的基于循环冗余码校验的特征分析，应用于需要用伪随机二进制数的应用中。基于vivado的程序设计(Linear feedback shift registers are usually used to perform signature analysis based on cyclic redundancy check in data compression circuits, and are applied to applications requir
ug908-vivado-programming-debugging
- ug908-vivado-programming-debugging(ug908vivadoprogrammingdebugging)
led流水灯
- 在vivado做的led流水灯，包括分频(Done in vivado LED water lamp, including frequency division)
lab1 Vivado Design Flow
- 适用于对verilog语言的初步学习，本文本就对RTL的编写，功能仿真，实现，布线，综合，以及生成比特流等环节进行了初步的描述。适合初学者学习。(For the preliminary study of Verilog language)
xuartps_intr_example
- microblaze uart vivado(vivado microblaze interrupt)
CPU-master
- 单周期CPU的Verilog源码实现，基于Vivado(Single cycle CPU Verilog source code implementation, based on Vivado)
pseudo_random
- 基于vivado Verilog的伪随机数发生器，采用LFSR算法，并对其进行了升级，使用反馈级联的思想，从最大周期为2^n提升为原来的3-5倍(Based on vivado Verilog pseudo random number generator, using LFSR algorithm, and upgrade it, using the idea of feedback cascade, from the maximum cycle of 2^n to 3-5 times the
蜂鸣器演奏
- 可以演奏音乐的vivado程序(the program that can play music basin in vivado IDE)
vivado_license_2016.4
- vivado 2016.4 license
test_5.0_tetris
- 基于Vivado实验平台，用Verilog语言编写的俄罗斯方块，可以在FPGA硬件上上下载运行(Based on the Vivado platform, the Tetris block written in the Verilog language can be downloaded on the FPGA hardware.)
User_IP
- 如何在 VIVADO 中创建用户自定义的IP(How to create user defined IP in VIVADO)
ug906-vivado-design-analysis
- ug906-vivado-design-analysis
Verilog秒表设计
- 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)