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Digital_system_design_example
- 数字系统设计实例.pdf,VHDL语言实现，7.1 半整数分频器的设计7.2 音乐发生器7.3 2FSK/2PSK信号产生器7.4 实用多功能电子表7.5 交通灯控制器 7.6 数字频率计.值得一看。-digital system design examples. Pdf, VHDL, 7.1-integer divider design Music Generator 7.2 7.3 2FSK/2PSK Signal Generator 7.4 Practical multi-functi
time_div
- IP 分频器 可以通过输入参数而自动调整分频数-IP divider input parameters can be automatically adjusted at the frequency
divhalf
- 本分频器不仅可以达到任意的整数分频，还可以达到半分频，例如3.5分频-The divider can be achieved not only arbitrary integer frequency, but also semi-sub-band can be achieved, for example, frequency of 3.5 points
music_disply
- 音乐播放器 中的数控分频器 后续还需要添加一个分频的电路-Music player in the follow-up of NC divider also need to add a sub-frequency circuit
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
clkdiv
- -- Clock divider of generic width (default = 4 bits) -- based on counter from Library of Parameterized Modules (LPM) -- Accepts clock signal at clk_in -- Output clk_out has frequency of clk_in/(2^width) -- Specify width in GENERIC MAP when in
fenpin27
- VHDL硬件语言系统时钟27分频程序，可用于各种时钟分频参考-VHDL hardware language system clock frequency of the program, 27 points can be used for a variety of clock divider reference
clock1
- 该代码实现的是使用VHDL语言编程实现的FPGA上的时钟分频。通过修改代码中的参数改变FPGA的输出时钟频率。-The code implements the VHDL language programming on the FPGA clock divider. Changed by modifying the parameters in the code of the output clock frequency of the FPGA.
verilog
- verilog分频程序，适合初学者，任意分频！-divider verilog procedures, suitable for beginners, arbitrary frequency!
fenpin
- 分频器程序，可以进行分频，精度高，很不错！-Divider program can be frequency, high accuracy, very good! Ha ha ha
源代码
- 这是内部有10位ADC的一个简单应用，这个电路最多测量30 V DC，可以应用在台式电源或各种系统中的面板仪表。 PIC16F676的内部adc与一个电阻网络分压器用于测量输入电压，用数码管来显示电压值，频率在50HZ左右 在原理图中的47K看到和10K电位连接分压器配置。在默认情况PIC微控制器ADC参考电压设置到VCC（+ 5V在这种情况下），分出最大射程30伏到5伏这样的分压器。(This is a simple application with 10 bit ADC insi
plj
- 使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6