搜索资源列表
rtl
- ddr controller in verilog-ddr controller in verilog...............
rtl
- SPI verilog RTL code
my_encode
- 利用verilog语言对一个编码器进行RTL的描述，实现编码器的逻辑功能。-RTL descr iption of an encoder verilog language, the encoder logic functions.
ps2_soc2
- PS2 Control Verilog RTL Code
DDR2Controller
- DDR2 SDRAM Control Verilog RTL Code
des.tar
- DES Encoder and Decoder Verilog RTL Code
spi_rtl
- 支持主从模式的、可综合的SPI verilog代码-Supports master and slave mode SPI communication module can be integrated RTL code
rs_decoder_31_19_6.tar
- RS Decoder RTL verilog Code
lcd1.tar
- LCD Control RTL Verilog Code
ss_pcm.tar
- PCM Verilog RTL Reference Code
t51.tar
- MCU 8051 Verilog RTL Code
uart16550.tar
- UART Verilog RTL Code
2_digital_clock
- 采用Verilog HDL RTL 描述完成数字钟，基于basys3，软件平台：vivado-Using Verilog HDL RTL to complete the descr iption of digital clock based on basys3 software platform: vivado
lab1 Vivado Design Flow
- 适用于对verilog语言的初步学习，本文本就对RTL的编写，功能仿真，实现，布线，综合，以及生成比特流等环节进行了初步的描述。适合初学者学习。(For the preliminary study of Verilog language)
eetop.cn_simple_spi
- spi 模块代码 RTL verilog(spi rtl code)
spi_verilog_master_slave_latest.tar
- spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)