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documentsoffifo
- 介绍FIFO的文章，关于同步FIFO或者异步FIFO-FIFO introduced an article on synchronous or asynchronous FIFO FIFO
shiyan3niu
- 1.利用FLEX10KE系列（EPM10K100EQC240-1X）的CLOCKBOOST （symbol:CLKLOCK）,设计一个2倍频器，再将该倍频器2分频后输出。 对其进行时序仿真。 2.设计一个数据宽度8bit，深度是16的 同步FIFO(读写用同一时钟)，具有EMPTY、FULL输出标志。 要求FIFO的读写时钟频率为20MHz， 将1－16连续写入FIFO，写满后再将其读出来（读空为止）。 仿真上述逻辑的时序，将仿真
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
fifo
- a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
aFifo
- 異步FIFO試作,寫入與讀取資料的時脈不同,藉此程式來達成-Test for asynchronous FIFO, write and read information on a different clock to the program to achieve
fifo_design
- 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
Async_fifo_Vijay_A._Nebhrajani
- Asynchronous FIFO Architectures - Designing a FIFO is one of the most common problems an ASIC designer comes across. This series of articles (by a popular author)is aimed at looking at how FIFOs may be designed -- a task that is not as simple as
yfifo
- 一个异步FIFO，自己写的。初学多交流学习进步快！-An asynchronous FIFO, write your own. Beginners to learn and exchange more rapid progress!
uartfifo
- 串口fifo的实现~实现了串口功能以及异步fifo，经过调试和功能仿真-The implementation of the serial fifo ~ serial port functionality as well as asynchronous fifo, after debugging and functional simulation
VFIFOzipe
- 用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
aasyn_fiffos
- verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件， -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
fifoVerilog
- 设计一个异步FIFO，完成数据平滑功能，FIFO的深度为256，宽度为8位，实时给出读空和溢出指示，写时钟为带间隔的100MHz，读时钟为5MHz，代码为了便于读阅，存放在word文档，可直接拷贝到quartus或者ise编译平台下使用-Design an asynchronous FIFO, complete data smoothing function, the depth of the FIFO 256, and the width is 8 bits, real read empty
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
FIFO
- 关于异步FIFO的原码程序，采用格雷码改善了二进制码带来的不足- ON划词翻译ON实时翻译 On asynchronous FIFO the original code procedures, the use of gray code improves deficiency caused by binary code
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.
Syn_FIFO
- 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
FIFO Design
- 异步fifo设计经典文章，可作为异步fifo设计基础导读(Asynchronous FIFO design classic article, can be used as the basis for asynchronous FIFO Design Guide)
fifo
- 学习Clifford_E论文之后完成的异步FIFO，可以完成异步时钟下的数据同步(After learning Clifford_E paper, the asynchronous FIFO can be completed under asynchronous clock data synchronization)
异步FIFO设计
- 经典的异步FIFO设计，First Input First Output的缩写，先入先出队列，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。(Classic asynchronous FIFO design)