搜索资源列表
free_IP_1
- 来自于OpenCores组织的开放IP核，非常专业，大牛编写。
u-uart
- UART verilog TX/RX OpenCores share
ethmac.tar
- Free ehternet mac using verilog downloaded in www.opencores.org
ata_latest.tar
- The OCIDEC (OpenCores IDE Controller) is a WISHBONE rev.B2 compliant ATA/ATAPI-5 host implementation. The ATA (AT Attachment) interface, also known as IDE (Integrated Drive Electronics) interface, provides a simple interface to low cost non-vol
Tgh_vhdl_lib_h
- Opencores的VHDLL元件库3.47版可直接使用。 -Opencores of the VHDLL component library 3.47 version can be used directly.
CAN(OpenCores)
- CAN控制器源码 Verilog-CAN controller source Verilog
spi_master_test
- SIMPLE SPI MASTER IP CORE FORM OPENCORES
I2c_opencores_v13.0
- i2c opencores module for Altera Avalon bus. Verilog.