搜索资源列表
MutiplierDesign
- 流水线乘法器,vhdl语言描述, 希望对大家有所帮助 -pipelined multipliers, vhdl language, we hope to help
VLSIASS2
- Self timed pipelined adder
CORDIC_ip
- cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined
FFT
- 流水线模数转换电路输出信号做fft后求SNR,SNDR的matlab程序-matlab fft program for SNR and SNDR of pipelined analog to digital converter（ADC）
file_encryption
- AES分组加密算法做的文件加解密演示, 采用多线程流水线方式对文件进行 读->加密/解密->写 操作.-AES block cipher algorithm for encryption and decryption so the paper presentations, the use of multi-threaded pipelined read on paper-> encryption/decryption-> write operation.
ADC
- Berkeley mixed-signal design. ADC simulation.
adc
- 1.5-b/s Pipelined A/D behavior model 以及功能包,包括SNR INL DNL测试- 1.5-b/s Pipelined A/D behavior model Include SNR INL DNL test progrems
071221088
- 实现一个简单的单周期流水线CPU，使用verilog语言开发 在quartus平台下运行-Implement a simple single-cycle pipelined CPU, using verilog language development platform running in quartus
MIPS_pipelined_analog_programming_code_VC
- MIPS pipelined analog programming code VC VC编程MIPS流水线模拟代码-MIPS pipelined analog programming code VC
thread
- 这是多线程编程，是线程的流水线模式编程，完全Linux编程-This is a multi-threaded programming is thread pipelined mode programming, complete Linux programming
x
- 某五级流水线CPU的设计原理图，含基本输入输出控制-traditional pipelined CPU design
pfftt_flp32_Ca
- 文件包为浮点快速傅立叶变换（32点）的汇编代码，运行在ADI的Visual DSP++平台上上，由于结合了并行流水线指令，该算法具有非常高的运行效率，能被广泛使用在高速数字信号处理方面。 -File package for the floating-point fast Fourier transform (32 points) assembly code, on the run in on ADI Visual DSP++ platform, due to a combination of
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
cpu
- MIPS流水线CPU的工作原理和设计方法-The design and implementation of the pipelined CPU
mips
- MIPS 五级流水线模拟系统，能读ASM代码，测试等-MIPS pipelined simulator
pipelined-CPU
- verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
CPUv1.6
- 简单的流水线CPU 课设做的 有实验报告 跟设计图-Simple pipelined CPU Lesson set up a lab report with design
SDF-DIF-FFT-pipelined
- vhdl code for pipelined single delay feedback radix 2 square FFT
chejiandiaodu
- 流水线型车间作业调度问题可以描述如下：n个任务在流水线上进行m个阶段的加工，每一阶段至少有一台机器且至少有一个阶段存在多台机器，并且同一阶段上各机器的处理性能相同，在每一阶段各任务均要完成一道工序，各任务的每道工序可以在相应阶段上的任意一台机器上加工，已知任务各道工序的处理时间，要求确定所有任务的排序以及每一阶段上机器的分配情况，使得调度指标(一般求Makespan)最小。下面的源码是求解流水线型车间作业调度问题的遗传算法通用MATLAB源码，属于GreenSim团队原创作品，博客上发布的是不完
simple-CPU
- 用C语言编写的简单处理器仿真器，CPU 仿真器-a simple pipelined processor simulater