搜索资源列表
FFT
- 流水线模数转换电路输出信号做fft后求SNR,SNDR的matlab程序-matlab fft program for SNR and SNDR of pipelined analog to digital converter（ADC）
ADC
- Berkeley mixed-signal design. ADC simulation.
adc
- 1.5-b/s Pipelined A/D behavior model 以及功能包,包括SNR INL DNL测试- 1.5-b/s Pipelined A/D behavior model Include SNR INL DNL test progrems
x
- 某五级流水线CPU的设计原理图，含基本输入输出控制-traditional pipelined CPU design
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
cpu
- MIPS流水线CPU的工作原理和设计方法-The design and implementation of the pipelined CPU
pipelined-CPU
- verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
CPUv1.6
- 简单的流水线CPU 课设做的 有实验报告 跟设计图-Simple pipelined CPU Lesson set up a lab report with design
SDF-DIF-FFT-pipelined
- vhdl code for pipelined single delay feedback radix 2 square FFT
chejiandiaodu
- 流水线型车间作业调度问题可以描述如下：n个任务在流水线上进行m个阶段的加工，每一阶段至少有一台机器且至少有一个阶段存在多台机器，并且同一阶段上各机器的处理性能相同，在每一阶段各任务均要完成一道工序，各任务的每道工序可以在相应阶段上的任意一台机器上加工，已知任务各道工序的处理时间，要求确定所有任务的排序以及每一阶段上机器的分配情况，使得调度指标(一般求Makespan)最小。下面的源码是求解流水线型车间作业调度问题的遗传算法通用MATLAB源码，属于GreenSim团队原创作品，博客上发布的是不完
simple-CPU
- 用C语言编写的简单处理器仿真器，CPU 仿真器-a simple pipelined processor simulater
cpu
- 16位五级流水线CPU no cache-16 five pipelined CPU no cache
DDR3L_H5TC4G4(8_6)3AFR
- The H5TC4G43AFR-xxA, H5TC4G83AFR-xxA and H5TC4G63AFR-xxA are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operatio
32bit_add_exercise
- 32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助-32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help
pipelined_fft_256_latest.tar
- 一个256流水线结构的FFT实现，用于FPGS实现，xilinix(A 256 pipelined structure of the FFT implementation, for FPGS implementation, xilinix)
ADC_Matlab_Model
- ADC模型，主要包括SAR ADC,sigma ADC,Pipelined ADC(adc model,including SAR ADC,sigma ADC,Pipelined ADC)
5-stage-pipelined-mips-master
- Its an processor with al u and blah blah blah
流水线乘法累加器设计
- 调用寄存器LPM,流水线加法器LPM,流水线乘法器LPM等模块实现一个8位流水线乘法累加器。(Call a register LPM, pipelined adder LPM, pipeline multiplier LPM and other modules to achieve a 8 bit pipelined multiplication accumulator.)