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loongson
- 龙芯2E处理器用户手册 中国科学院计算技术研究所 意法半导体公司 2006年 9 月 龙芯2E处理器是一款实现64位MIPS III 指令集的通用RISC处理器。龙芯2E的指 令流水线每个时钟周期取四条指令进行译码，并且动态地发射到五个全流水的功能部件 中。虽然指令在保证依赖关系的前提下进行乱序执行，但是指令的提交还是按照程序原 来的顺序，以保证精确中断和访存顺序执行。 -Godson 2E processor user manual CAS Institute of Comp
~CDDBNY834200PDF
- 探讨RISC32处理器设计中三个关键问题包括多媒体指令集扩展设计、流水线微结构优化设计以及使RISC32成为一个真正IP核的其他相关设计问题-explore RISC32 processor design three key issues, including the expansion of multimedia instruction set design, pipelined micro-structural optimization design and make RISC32 beco
pipeline_10b_adc
- 10bit pipelined adc in matlab
BoothMultiplier
- A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier
platforms
- A Pipelined Implementation of AES for Altera FPGA platforms.doc
TheResearchoftherealtimesignalprocessingofSARbased
- 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置 存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高 效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配， 满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法 实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging ar
pipeline_3bADC
- 3bit pipelined ADC in matlab
pipeline_6bADC
- 6bit pipelined adc in matlab
fingerprint11
- pdf for fingerprint from ieee include: PIPELINED MINUTIAE EXTRACTION FROM FINGERPRINT IMAGES A Novel Principal Component Analysis Neural Network Algorithm for Fingerprint Recognition in Online Examination System Processing of Distorted Finger
222
- pipelined multiplier accumulator architecture
VLSI_Architectures
- 超大规模集成电路算法和流水线架构设计，高级IC进阶-VLSI algorithms and pipelined architecture design, advanced IC Advanced
fft2
- a 4 point fft is designed using a pipelined architecture
Wave-Pipelining-A-Tutorial-and-Research-survey.zi
- Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined arch
Verilog_EX
- 移位乘法器/流水线乘法器，流水线结构的基本应用-Pipelined multiplier
aes_pipe_latest.tar
- VERILOG IMPLEMENTATION OF PIPELINED AES ALGORITHM
ASE
- 可重构平台下AES算法的流水线性能优化，讲解比较到位，抛砖引玉可以-Reconfigurable platform performance optimization of pipelined AES algorithm, to explain more in place, so you can
256MbSDRAMx32
- • PC100 functionality • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal banks for hiding row access/pr
FSK_Rx
- Pipelined FSK correlation detector
Design-and-implementation-of-High-Speed-Pipelined
- Design and implementation of High Speed Pipelined DDR SDRAM memory Controller
184081165-16-Bit-Wave-Pipelined-Sparse-Tree-RSFQ-
- In this system, we discuss the architecture, design, and testing of the first 16-bit asynchronous wave-pipelined sparse-tree superconductor rapid single flux quantum adder implemented using the ISTEC 10 kA/cm 2ADP2.1 fabrication process. Compar