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A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
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A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
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As the source code name, this code is writing in Verilog and also inside the folder there is a c code to see the simulation results from verilog.
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8选一选择器的verilog实现，运行通过仿真！-8 election selector verilog implementation, running through simulation!
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