搜索资源列表
IIC_Verilog1
- 功能：IIC通信的Verilog描述写法； 包含有通信部分（写数据和读数据），分频时钟SCL，和顶层模块。-Function: IIC communication Verilog descr iption written contains the communication part (write and read data), sub-frequency clock SCL, and the top-level module.
ps2mouse
- 基于FPGA的PS2鼠标驱动，代码采用verilog语言。-the driver of ps2 mouse
Endat2_1_freq
- 用verilog实现endat2_1驱动,并用signalTap捕捉信号。-Using verilog achieve endat2_1 drive and use signalTap capture signal.
lsd_1
- 流水灯，即跑马灯，利用verilog语言进行控制，和大家相互学习学习-Flowing water light, namely entertaining diversions, use verilog language control, and we learn from each other to learn
USBSAMPLE
- 使用VERILOG语言编写的CY7C68013与FPGA程序，FPGA采用ALTREA公司-Use VERILOG language program CY7C68013 and FPGA, FPGA using ALTREA company
SHAH1
- ACO files for the verilog desciption
4weijianfaqi_verilog
- 四位加法器的verilog实现，用VHDL语言，附tb.v。-Verilog achieve four adder, using VHDL language, with tb.v.
qiduanyimaqi_verilog
- 七段译码器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-Seven segment decoder verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
sanbayimaqi_verilog
- 三八译码器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-Thirty-eight verilog decoder implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
sixuanyiduoluxuanzeqi_verilog
- 四选一多路选择器的verilog实现。VHDL，单片机开发程序，数字逻辑与处理器基础实验，你懂d。-4 election more than one way selector verilog implementation. VHDL, MCU development program, the digital logic and processor basic experiment, you know d.
FPGA-Verilog-I2C
- FPGA描述I2C协议过程，采用Verilog语言编写，压缩包里含有完整的代码（已经综合仿真），仿真图-FPGA I2C protocol process descr iption, using Verilog language, compressed bundle contains the complete code (already integrated simulation), simulation map
EEPROM_FUNC
- VERILOG实现EEPROM的读写时序-fpga with verilog control the eeprom read and write
S27_SDRAM_IP
- SDRAM 驱动读写demo，用verilog写的上板测试过-SDRAM verilog
4_led_test
- 此文件的功能是led驱动，主要的用途是驱动LED等点亮(The function of this file is led drive, the main purpose is to drive the LED and other lights)
axi slave model
- axi slave model,verilog源码