本程序是用VHDL语言，非整数分频的一个实现， fenpin.vhd为主程序-this procedure is used VHDL, non-integer frequency of a realization of the main procedures fenpin.vhd

任意分频VERILOG实现，包括奇数分频、偶数分频，与小数分频等等。-Arbitrary frequency VERILOG implementation, including the odd frequency, even frequency, and fractional frequency division, etc..