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CODE.rar
- DDR2源代码 DDR2源代码 DDR2源代码,ddr2 source code ddr2 source code ddr2 source code
LJQ
- 本压缩包是我常用连接器PCB封装,希望对你有用.包括FPC连接器、四合一卡座SD+MS+MMC+MS、SD卡座 push push型、mini pci e 52pin连接器、TF卡座、DDR2 200PIN等连接器。-The compression package that I used the connector PCB package, want to be useful to you. Including FPC connectors, four are CARD SD+ MS+ MMC+
WSPD_NEW_K8M890_SIS671_RS690
- 该软件实现自动写入01到127(base 0)中(DDR2),根据参数决定是否比对所有的SPD数据(需要 数据文件) 运行环境: dos K8M890, SIS671, RS690 数据文件 数据文件编码: SM212NG08EAF.txt -> M212G08EA.txt ^^^^ ^ ^^^ ^^^^ 参数说明： -h 调用帮助(退出) -p 写入passcode,并验证一次 -cmp 读取并校验所有的SP
Micron_DDR
- DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
TMS320C6455
- tms320c6455 High-Performance Fixed-Point DSP TMS320C64x+™ DSP Core Enhanced VCP2 Enhanced Turbo Decoder Coprocessor (TCP2) 64-Bit External Memory Interface (EMIFA) Four 1x Serial RapidIO® Links (or One 4x), DDR2 Memory Controll
2416
- S3C2416JTAG调试初始化ddr2文件-a S3C2416 obey file to init ddr2 sdram
AllegroDDR2
- DDR2讲座allegro 资料不错 可以下载学习-DDR2 PPT reference 资料不错 学习
npi_write
- 从FPGA向DDR2写入数据。采用NPI接口。单字写入。是用Verilog HDL 写的-Write data from the FPGA to DDR2. Using NPI Interface. The word is written. Is written using Verilog HDL
MICRON_2048Mb_ddr2
- micron ddr2 sdram verilog model and documents
nios_DDR2
- NIOS的DDR2SDRAM工程文件，帮助理解DDR2在SOPC中的设置方式-Of NIOS DDR2SDRAM engineering documents, to help understand the DDR2 is set up in the SOPC
DDR2Controller
- DDR2 SDRAM Control Verilog RTL Code
1Gb_DDR3_SDRAM
- DDR2 specification protocol for ddr design
Atmel-SAMA5D3x-DDR-Application-note
- Atmel SAMA5D3X DDR,DDR2,LPDDR2应用说明.-Atmel Microcontroller SAMA5D3x DDR2 LPDDR2 Application note
t2_hpc
- DDR2的控制器设计，完成功能的验证，以及仿真测试，(DDR2 controller design, complete function verification, and simulation test,)
NTC-DDR2-1G-G-R21
- DDR2设计文档资料，参考手册，详细介绍DDR2规格参数及设计参数，供参考(DDR2 design documentation, reference manual, detailing the DDR2 specifications, parameters and design parameters for reference)
DDR2_Controller-master
- DDR2_Controller-master
DDR2_Control
- 本人用verilog编写的DDR2控制器，经测试可用。(I am prepared to use verilog DDR2 controller, the test is available.)
内存pdf
- MT47H256M4 内存芯片手册 对cpu连接内存时序要求理解 ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */ | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */ | AT91C_DDRC2_TXSNR_(27) /* 19
5692-thphn72
- modding ddr 2 sd ram to 800mhz