搜索资源列表
fpga_div
- Altera的FPGA，设计的硬件除法器-Altera' s FPGA, the design of the hardware divider
restoring
- restoring除法器设计 经典算法了，可以仿真通过-divider restoring a classical algorithm design, simulation can be adopted
Sequentialdivider
- program to perform sequential divider in vhdl
38.58
- 基于VDHL的38译码器的实现与58分频器的实现 FPGA主芯片：CycloneII EP2C35F672C6-Based on VDHL decoder 38 with the divider 58 to achieve the main FPGA chip: CycloneII EP2C35F672C6
Freq_Divider
- frequency divider using verilog
divider_latest.tar
- floating point divider
frequency-divider-graphic-design
- 数字系统EDA 多级分频器图形设计 熟悉和掌握MAX+PlusⅡ的编译、仿真操作。-The multi-level divider graphic design of digital systems EDA familiar with and master MAX+Plus Ⅱ compilation, simulation operation.
FPGAfrequency-divider
- 一种基于FPGA的分频器实现，讲的很详细，很实用，希望能帮助您。-A kind of the frequency divider based on FPGA realization, speak very detailed, very practical, the hope can help you.
Three-divider
- 用verilog硬件描述语言实现的三分频器-Three divider
divider
- verilog的除法器 有多重方法 很适合初级者阅读-verilog divider multiple method is very suitable for beginners to read
divider
- 时钟分频,改一下参数就能立即实现电子电路的时钟分频，用于EDA程序设计-clock divider
DGITAL-DIVIDER
- Digital divider details
float-point-divider
- 基于FPGA的单精度浮点除法器vhdl设计程序,分模块程序。-FPGA-based single-precision floating point divider vhdl design program, sub module program.
greatest-common-divider
- 一个用于计算两个数的最大公约数的逻辑算术单元-an arithmetic logic unit which is used to calculate the greatest common divider of two numbers
divider
- 用Verilog实现的除法器，通过了编译和测试，可以放心使用。-Divider implemented using Verilog, by compiling and testing, you can rest assured that use.
divider
- 输出任意频率的分频器，使用verilog语言实现-The divider wright using verilog
design-of-divider-
- 应用FPGA软件编写的关于除法器的小程序，适合初学者学习，很实用，而且很简单，-FPGA application software prepared by the divider small program for beginners to learn, very practical and very simple, Ha ha ha
divider
- a vhdl code for divide operation in fpga spartan6
Divider
- this is divider for verilog
RPWM-matlab
- clock divider program by using VHDL