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spi_master
- SPI wishbone master and verification environment
wb-ddr
- 基于Wishbone总线的DDR控制器. -A wraper of DDR controller for wishbone bus.
spi_v
- 基于wishbone总线的spi串口控制器-a spi compilant serial port controller based on wishbone on-chip bus
ata_latest.tar
- The OCIDEC (OpenCores IDE Controller) is a WISHBONE rev.B2 compliant ATA/ATAPI-5 host implementation. The ATA (AT Attachment) interface, also known as IDE (Integrated Drive Electronics) interface, provides a simple interface to low cost non-vol
yadmc_latest.tar
- 基于wishbone总线的sdram控制器-sdram control with wishbone interface
i2c
- WISHBONE revB.2 compliant I2C Master controller Top-leve
Ethernet_MAC_10-100-Mbps_latest.tar
- The Ethernet IP Core is a MAC (Media Access Controller). It connects to the Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other. The core has been designed to offer as much flexibility as possible to all kinds of applications
wishbone
- wishbone片上总线系统设计，实现基本的共享总线实例。并用modelsim进行仿真。-wishbone chip bus system design, to achieve the basic shared bus instance. And use modelsim simulation.
wb_master
- this the wishbone master interface to connect with wishbone slave and a clock module-this is the wishbone master interface to connect with wishbone slave and a clock module
openmips
- 一个开源mips处理器verilog 源码-wishbone interface wishbone interface
wishbone
- gives back a datavector containing locations and angles of a double wishbone suspension
draw_wishbone
- draws a car with a double wishbone suspension geometry
wishbone_vip
- WISHBONE VIP IN system verilog
ahb2wishbone_latest.tar
- AHB to wishbone bridge verilog
dma_rtl
- 该代码实现了一个基于Wishbone总线协议的DMA控制器，由于SOC可集成的模块越来越多，本文设计的DMAC包含了31个可编程的DMA通道，能够处理多个DMA传输请求。由于数据在Wishbone总线上传输，在总线接口方面，本文设计的DMAC提供了两个既可以作为主机接口又可以作为从机接口的Wishbone接口。当有多个外设同时发出DMA请求时，本文设计的DMAC采用循环优先级和动态优先级相结合的方式，实现了通道仲裁器二级仲裁的功能。为了提高传输效率，本文设计的DMAC不仅支持数据块的传输，还支持