搜索资源列表
sdr_sdram_control
- 一个SDRAM控制器，verilog语言设计，并在ISE上仿真实现。（内部包含多个verilog程序）-sdram-controller,use verilog langguage,it s run sucessfull
Sdram_Control_4Port
- SDRAM控制器HDL实现，sdram为美光公司的-sdram controller
SDR-SDRAM-ctl1
- SDR SDRAM控制器，FPGA vhdl代码-SDR SDRAM Controller
sdram_all
- sdram 控制器的verilog 实现，包括用户逻辑和控制器的设计-SDRAM controller Verilog realization, including user logic and controller design
testbench
- ddr sdram controller datd module source code
sdram
- 在ISE开发环境下的单速率SDRAM简单读写控制器设计，用的是verilog硬件描述语言-ISE development environment in a single-rate SDRAM controller read and write simple design, using the verilog hardware descr iption language
xilinx_sdcontroller
- xilinx公司的sdram控制器代码及说明文件-sdram controller of xilinx, codes and notes
module
- SDRAM控制器源代码，已经过调试，可以试用一下。-SDRAM controller source code, has been testing, you can try.
sdram_control
- sdram 控制器的源代码及说明文档，综合，仿真。是一个很好的sdram控制器学习资料-provide sdram controller source code and documentation, integration, simulation. Is a very good learning materials about sdram controller
FPGAbasedSDRAMControll
- 基于FPGA的SDRAM控制器 Realization FPGA-based SDRAM Controller with Verilog-FPGA-based SDRAM Controller Realization FPGA-based SDRAM Controller with Verilog
NewFolder
- sdram controller code
SDRAM_VHDL
- VHDL SDRAM Controller
eetop.cn_SDRAM
- 实现sdram控制器的verilog代码，很好的学习资料-The sdram controller verilog code, very good learning materials
sdr_ctrl
- SDRAM控制器源码 Verilog描述-SDRAM controller Verilog source descr iption
SDRAM_Modelsim
- 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
SDRAM
- SDRAM controller: it contains a SDRAM controller writtern in verilog language. It is a interface between microprocessor and SDRAM device.
SDRAM
- SDRAM控制器的VHDL语言描述及仿真-SDRAM controller
mem_interface_top_ddr_controller_0
- 在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。-DDR controller
SDRAM_ctrl
- sdram controller in vhdl
sdram_uart
- sdram控制器的设计，包括 ：初始化、刷新模块、读写模块、命令解析模型的编写，通多串口发送接收数据验证设计的正确性(The design of SDRAM controller includes initialization, refresh module, read and write module, command parsing model, and the correctness of data verification design by sending and receiving