搜索资源列表
testbench
- ddr sdram controller datd module source code
alu
- ALU modeling verilog codes and testbench
TESTBENCH
- 一个关于testbech写法的文档，很经典-A written document on the testbech very classic
mem-ctrl-rtl
- 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
multiplier8x8
- 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
vhld_tb_latest.tar
- 一个VHDL的测试平台，可以用来验证MircroProcessor，有完备的文档和代码。-A testbench based on VHDL language, you can apply it to verify a simple mircroprocessor, include complete ducoment and sources
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
FPGABitcoinMiner
- 比特币的FPGA挖币机中SHA256的核心代码及测试用例，适合于自己开发比特币挖币机-vhdl based SHA256 computation code and testbench for bitcode miner. For developers that build their own mining machines
SDRAM_Modelsim
- 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
pr_step7-(1).vhdl
- 8位alu 附上testbench以供仿真-8 alu attach testbench for simulation
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
Arbitrary-_odd_-frequency_VHDL_code
- 任意奇数分频的VHDL代码和testbench测试VHDL代码，经过ISE的ISim仿真工具测试，模块功能准确有效，特此分享！-Arbitrary odd frequency of VHDL code and test VHDL testbench code, after the ISE ISim simulation tool to test module functions accurately and effectively, would like to share!
Multiplier
- 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is
1
- Hi This is an example of file ZIP Best regards