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verilog
- 设计可以对两个运动员赛跑计时的秒表:(1)只有时钟(clk)和一个按键(key),每按一次,key是持续一个时钟周期的高电平脉冲 (2)秒表输出用0-59的整数表示 (3)key: (A)按一下key,开始计数; (B)第一个运动员到终点时第二下key,记住时间,继续计数; (C)二个运动员到时按第三下key,停止计数; (D)然后按第四下key,秒表输出第一个运动员到终点的时间,即按第二下key时记住的计数值; (E)按第五下key,秒表清0。 -Design
Basic-sequential-logic
- 用Verilog语言实现D触发器、累加器的功能-D flip-flop, the function of the accumulator using Verilog language
Verilog1
- 实现了cic分频功能,分频系数D可变2~32,代码用verilog编写,其中输入数据写入主程序中,便于后人testbench的编写-Cic divide divider coefficient D variable from 2 to 32, the code is written in verilog input data is written to the main program, to facilitate future generations testbench preparation
dff-n-d-latch
- Dlatch and D Flipflp code with testbench in Verilog
shiyanjiu
- 学习verilog时写的D触发器实验代码(D flip-flop experimental code written when learning Verilog)
shiyan9
- 学习verilog时写的D触发器源代码,供大家参考(D flip-flop experimental code written when learning Verilog)