搜索资源列表
cic
- verilog码写的CIC滤波器的程序，包括4倍抽取CIC滤波器和内插的CIC滤波器两个
ImproveddesignofCICfilteranditsimplementationonFPG
- 。介绍了内插器和抽取器这2种CIC滤波器各自的结构与性能，从数学上分析了其性能及其与FIR 滤波器的关系，从频域上展示了其本质。并讨论其内部寄存器的最小位宽与溢出保护，最后介绍了抽取器与内插器分 别在FPGA上的一般实现方法，并指出了一些提高实现性能的措施与建议
cic1s2
- 单级CIC2倍内插滤波器，用verilogHDL实现
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
52252276494
- 基于多相结构的内插脉冲成形滤波器的DSP 实现-Based on the multiphase structure of interpolation pulse shaping filter DSP realization
cic_intp_64_four
- 4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
Cic_Interpolator
- 实现了2级cic滤波器的功能，其中内插32倍，即实现了32倍的2级cic内插滤波器-Realize the level 2 cic filter function, including 32 times interpolation i.e. the 32 times the level 2 cic interpolation filter
vhdl
- cic 滤波器，vhdl代码 ，内插与抽取-cic filter ，vhdl code about decination and interpolation
filter_lpm_shaping
- 4倍内插值的fir成型滤波器，语言vhdl，工程已建立，可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
interpolation_shaping_filter
- 内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用-Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly
36-tap-interpolation-coefficeint
- 36阶内插值滤波器系数生成Matlab程序-A little code for generating 36-tap-interpolation-coefficient.
Lab4
- 该实验室会议的目的是要实现一个可配置的FM-AM数字调制器的数据通路。它是由一个CIC内插滤波器及可配置的FM-AM块。调制器信号以48kHz被取样，并且由CIC内插滤波器的装置内插高达96MHz的。在FM-AM配置块适用于96 MHz的时钟-The aim of this laboratory session is to implement the data-path of a configurable FM-AM digital modulator. It is composed of
interpolate4
- 调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据-4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data