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mydesign.rar
- 基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具， 各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。 ,FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simu
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
SDR
- 直接序列扩频通信的Verilog仿真代码，在Quartus II中实现。-Direct sequence spread spectrum communication Verilog simulation code, implemented in Quartus II.
DSSS
- 基于FPGA的我直接扩频序列发射机的quarters代码，-direct sequence transmitter
VHDL_DMF
- Vhdl实现扩频通信匹配滤波器，书上打下来的,打了好久.-VHDL realization of spread spectrum communication matched filter, books, playing down, playing for a long time.
Sender
- 直序扩频通信发送部分的源代码，用verilog编的，包括信源模块、扩频模块、极性变换模块和DDS调制模块-Direct sequence spread spectrum communication sent part of the source code, compiled with verilog source modules, spread spectrum modules, polarity transform module and DDS modulation module
QPSK_DSSS
- 该程序使用verilog语言，编写了QPSK-DSSS系统的发端，主要模块包括对同相分量和正交分量的扩频，通过根升余弦滤波器，以及与载波相乘等模块。-The program uses the verilog language, written QPSK-DSSS system, the originator, the main modules include in-phase and quadrature components of the spectrum, through the root
扩频通信的Verilog工程
- 扩频通信的Verilog工程，对从事无线通信的工程人员有参考作用。(Spread spectrum communication Verilog project, engaged in wireless communications engineering staff reference.)
m-test
- 产生小m序列，用于扩频系统中，仿真测试正确，反馈级数为4(Generating m sequences)