搜索资源列表
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
FPGA
- 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计 -The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code descr ipt
CoreAES128
- Full AES Simulation Code
AES!
- AES algorithm very good code tested in xilinx ise tool
sbox
- verilog code for s-box generation for AES algorith
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
aes-vhdl
- this file contains vhdl code for aes
aes_pipe
- 流水线AES加密VHDL代码，代码规范，值得参考- The VHDL code of Pipelined AES encryption
new
- vhdl code aes algorithm newly modified
des_vhdl_code
- decription aes using vhdl code
dec_aes
- decription aes vhdl code for fpga
avs_aes_latest
- This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA
Coding Files
- We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
aes-master
- aes master by vhdl code and decode