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beijingdaxue_verilog_pdf
- 北大的verilogHDL教程，从潜入深，逐步深入的讲解，但是许多重点都被提到了，是不错的教程。-Peking University verilogHDL tutorial from dive deep, and gradually in-depth explanations, but many have been referred to the focus, is a good tutorial.
LPC2148
- arm7开发资料中文资料开发大全，可以供初学者进行深入分析-development of Chinese information to develop data arm7 Guinness, you can conduct in-depth analysis for beginners
USB
- 一本关于USB设备驱动开发深度解析，作者宋宝华，其中关于usb驱动的开发很详细深入，使用高级工程师。-A USB device driver development on the depth of analysis, the author Song Baohua, which is on the usb drive for more in-depth development, the use of senior engineer.
Verilog
- 针对Verilog语言，提供了135个经典的示例程序代码，从简单到复杂，一步步的深入。-For the Verilog language, providing 135 classic example code, from simple to complex, step by step in depth.
1
- 基于51单片8路抢答器，可以扩展到16路，用数码管显示，仿真图可仿真。-c language-depth analysis
fifo
- 详细介绍了fifo深度计算的方法，fifo深度的计算是面试中常被问到的问题！-Fifo depth details of the method of calculation, fifo depth calculation is frequently asked interview questions!
GLCD_Extended_by_CNR
- This file contains drivers for using a KS0108 based 128x64 pixel GLCD. This "Extended_GLCD.c" driver based on, "GLCD.c" driver can be found in CCS installation folder. The driver treats the upper left pixel as (0,0). // The NEW functions added b
programming-for-linux-c
- 全面、系统、深入探讨linux下c程序设计的核心技术与思想，采用案例展示开源原件设计的思想-Comprehensive, systematic, in-depth study under linux c programming the core technology and ideas, using the open source case shows the original design ideas
FIFO
- verilog 实现FIFO存储功能，八位数据宽度，16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
Verilog_integer_reg
- 深入探讨verilog中integer与reg两者的区别，从综合与实现的角度介绍-Depth in the integer and reg verilog difference between the two, from the point of introduction and implementation of comprehensive
LectureNote
- 高级Xilinx FPGA ISE设计教程，详细讲解优化Xilinx设计结构改善时序，减少implementation时间，减少调试时间，片上验证以及调试等FPGA设计深入环节，是深入理解FPGA设计的不可多得的好书。-Advanced Xilinx FPGA ISE design tutorial, explain in detail the structure of the Xilinx design optimization to improve timing, reduce implem
chapter4
- IARfor ARM深入例程，具有很好的学习帮助，定会助你成长迈进一大步！-IARfor ARM routine in depth, with a good learning assistance, will help you grow a great step forward!
123765
- 有人也许和我一样比较心急，想尽快知道如何去写一个具体的驱动程序，这里，假设您对驱动程序已经有比较好的了解，告诉大家一个快速上路的方法。当然，如果您有足够的时间我建议在动手之前还是深入了解一下CE整个系统架构-Some may like me more anxious, as soon as possible to know how to write a specific driver, here, assuming you have good drivers understand the roa
789123
- 有人也许和我一样比较心急，想尽快知道如何去写一个具体的驱动程序，这里，假设您对驱动程序已经有比较好的了解，告诉大家一个快速上路的方法。当然，如果您有足够的时间我建议在动手之前还是深入了解一下CE整个系统架构-Some may like me more anxious, as soon as possible to know how to write a specific driver, here, assuming you have good drivers understand the roa
FIFO-verilog
- 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design,
perflab-handout_2011111116234086
- 深入理解计算机系统C语言程序代码，描述对于bom算法的实现与理解-In-depth understanding of the computer system C language code that describes the algorithm for the realization and understanding of the bom
datalab-handout_2011923211157187
- 深入理解计算机系统C语言程序代码，描述对于datalab算法的实现与理解-In-depth understanding of the computer system C language code that describes the algorithm for the realization and understanding of the datalab
bvbsoft.com_noxgvqwp
- 深入理解计算机系统C语言程序代码，描述对于bvbsoft算法的实现与理解-In-depth understanding of the computer system C language code that describes the algorithm for the realization and understanding of the bvbsoft
4Verilog-FIFO
- FIFO的简单编程，该FIFO的深度为4，宽度为32，其接口类型见文件中的图标及其注释。-This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example,
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p