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Lab5_x7seg
- 7段显示管的设计与实现.nexy3开发板。在2个7段显示管上显示一个2位的十六进制数，本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3.
Lab6_decode38a
- 3-8译码器的设计与实现.3-8译码器的真值表，本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3
S16_ADC
- 用Verilog HDL语言编写的AD转换器，可以再Xilinx芯片实现，用ISE软件环境下开发-Using Verilog HDL language AD converter, you can then Xilinx chip, with the ISE software development environment
cordic
- ise下用verilog实现的cordic算法的实现程序-ise under cordic algorithm verilog achieved with implementation of the program
run_led
- Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
lab2
- 熟悉XUPV2P实验开发平台。熟悉掌握Verilog HDL语言并能用其建立基本 的逻辑部件在Xilinx ISE平台进行输入、编辑、调试、仿真-Familiar XUPV2P experimental development platform. Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for entering
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s
20140825
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
FIR
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
W25Q16_verilog_ise
- 一个基于w25q16的四通道flash读写操作控制器，spi传输。verilog语言编写，在ise的chipscop上验证可行，仅作学习参考-this is refrence about flash w25q16 controller ，writed by verilog
Traffic-Controller
- 本代码为基于Spartan6的verilog交通控制灯代码，在ISE软件中仿真成功。-The code for the verilog code Spartan6 traffic control lights on in the ISE software emulation success.
Adder
- 本代码为用三种方法实现verilog加法器代码，在ISE中基于Spartan6仿真成功。-This code is used three methods to achieve adder verilog code, based on the success in the ISE Spartan6 simulation.
Booth4b
- booth 4 bits programmed by verilog and simulated using ISE software and no implemented
car
- 基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器-Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors
IIR
- 用Verilog实现一个IIR滤波器，并在ISE里面仿真。-Achieve an IIR filter with Verilog and simulation in ISE inside.
vga
- VGA控制器，Verilog描述，ISE工作环境-VGA controler
uart
- 利用xilinx 公司的ise软件基于verilog HDL实现UART控制程序-based on the xilinx ise and use verilog HDL language to achieve the purposes that control the uart.
led_shift
- 在xilinx的ISE上写的LED灯移动的verilog程序-a verilog code for led-shifting which writed with ise 14.2