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Verilog_code_for_AWGN.rar
- verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。,verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.
medianfilter
- 图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写-Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language
MATLAB-and-verilog
- 1 采用正弦波，方波进行同步调制，实现调制信号、已调信号、解调信号的波形、频谱以及解调器输入输出信噪比的关系。 2 采用Verilog语言编写有符号的五位乘法器 3 实现数字与模拟调制-A sine wave, square wave synchronous modulation to achieve the modulation signal, the modulated signal, the demodulated signal waveform, spectrum and sig
digital-filter
- Verilog语言综合的固定频率的数字滤波器，用于滤除夹杂在固定频率信号上的杂波信号，包含了Quaetus工程和仿真文件。-Verilog language integrated fixed-frequency digital filter for filtering out mixed signals at a fixed frequency noise on the signal contains Quaetus engineering and simulation files.
gwnseq
- verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）-verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence
uart_tx
- 用Verilog实现通过上位机向串口发送多帧数据，并具有抗噪功能-Implementation serial port receive more frame data by software use Verilog, and has the function of the resist noise
AWGN_VerilogDesign-master
- 加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用-Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly
noise
- 使用FPGA搭建NOISE||内核，在内核基础上进行工程建立。(Using the FPGA to build NOISE || kernel, based on the kernel to build the project.)
Verilog语法下载
- 介绍verilog语法，详细讲解了Verilog的易错点难点，有较好的知道效果(It is used to measure noise and detect road noise pollution. It is accurate and has good effect.)
elecfans.com-verilog教程书
- 从入门到精通，从简单到难，带你轻轻松松玩转FPGA(It is used to measure noise and detect road noise pollution. It is accurate and has good effect.)