搜索资源列表
bmp2bin
- 将BMP图像信息转换成coe文件,用与Xilinx fpga的ROM初始化-turn the information of BMP to coe document for Xilinx FPGA
SSD_MULTIPLEXING
- four seven segment displays are in multiplexing implemented on xilinx FPGA XC3S50
AD80305
- 一种基于xilinx FPGA S6,verilog 实现AD80305输入输出接口配置，可参考-Based xilinx FPGA S6, verilog realize AD80305 input and output interface configuration, refer to
CLK_GEN
- Xilinx FPGA时钟倍频电路，使用内部全局时钟、DCM，可参数化。-Clock Generater for Xilinx FPGA
HWL_ASYNC_FIFO_DRAM_BA
- asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
xilinx_usb
- 基于xilinx FPGA 的USB开发，实测好用-xilinx USB development, available
MATLAB-and-FPGA
- 以Xilinx公司的FPGA为开发平台，采用MATLAB及VHDL语言为开发工具，详细阐述数字通信同步技术的FPGA实现原理、结构、方法以及仿真测试过程-In Xilinx s FPGA development platform, using MATLAB and VHDL language development tools, elaborated synchronous digital communications technology FPGA implementation princip
xilinx_PCIeLogiCore
- 基于xilinx fpga的PCIE逻辑IP核-thisis a xilinx_PCIeLogiCore
xapp1205-high-performance-video-zynq
- Xilinx FPGA平台Zynq ZC702下AXI vdma IP核应用工程。-An Axi vdma ip application project based on Xilinx Zynq ZC702 platform.
vga256
- 本代码是用于Xilinx FPGA 开发板 开发实验的 vga256 verilog源代码 -This code is used for Xilinx FPGA development board developed experimental vga256 verilog source code
Quadrotor_control
- 基于xilinx FPGA的四旋翼简单控制系统ISE14.1工程文件。于spartan-6上验证成功。-Quadrotor control system based on Xilinx FPGA.
drv_dm900
- 这是去年我编写的基于xilinx FPGA的MAC IP 核开发的驱动DM9000的源代码。基于Verilog 语言。-This is the last year I wrote based on xilinx FPGA the MAC IP core developed DM9000 driver source code. Based Verilog language.
XC3S400TQ144
- Just little program for xilinx FPGA. It is can be used as a example for education.
Xilinx-V7-FPGA
- xilinx v7 FPGA 的型号参数描述，利于读者进行FPGA的选型和编程-the descr iption of xilinx v7 FPGA,you can choose the right type of the FPGA
1rar
- Xilinx FPGA 部分封装原件库文件-Xilinx FPGA intlib
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
xapp524
- xilinx FPGA 与高速ADC LVDS接口的范例程序-xilinx FPGA ADC LVDS interface
sp6_BoardTest
- 针对xilinx spartan6芯片做的测试板测试用例-xilinx FPGA product SPARTAN6 test example
ZHWX
- DDS 产生正弦信号，OOK，AM三种波形。 使用xilinx FPGA VHDL-DDS. Resulting in sinusoidal signal, OOK, AM three waveforms. Using xilinx FPGA VHDL.
udpip
- 赛灵思XILINX FPGA verilog写的UDP/IP协议，可用。-I am prepared to use verilog UDP protocol, the test is available.