搜索资源列表
SPWM
- VHDL采用自然采样法写的SPWM,里面有正弦表,可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
i2c-verilog
- 可进行i2c读写操作I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable-it can write and read codes in i2c.I2C is a two-wire, bi-directional serial bus that provides a
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
lcd1602
- verilog编写的LCD1602控制源代码,能够显示一串字符。-verilog source code written LCD1602 control, can display a string of characters.
Verilog
- 基于Verilog HDL的通信系统设计一书的源代码,大家可以下载,参考一下-Verilog HDL-based communication system design of the book source code, you can download, refer to
RS485EN
- RS485的双向通信处,正在为此头疼的同学们可要注意了,这个可以解决你们双向通信过程中的很多问题哦-Two-way RS485 communications, the headache is to this end they' ll pay attention to the students, this two-way communication you can solve many problems in the course of oh
arccos
- 一个求反余弦的cordic算法,整个工程。包括仿真。可以直接打开。-An inverse cosine of the cordic seeking algorithms, the whole project. Including the simulation. Can be directly opened.
10100MIP
- 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码,可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
clock
- verilog 实现的跑表程序。可以对这个程序加以修改,可是显现电子钟的设计。设计可以根据需要实现分秒。同时可以改成是LED的跑等程序。功能强大的很!-verilog implementation stopwatch program. This procedure can be modified, but the show clock designs. Design can be according to the need to achieve every second. At the same
ram2
- RAm的 verilog描述,在Quartus中验证正确,可根据程序改成其他参数-Verilog descr iption of RAm in Quartus verify correct procedures can be changed in accordance with other parameters
DAC8812
- DA转换,Verilog HDL 编的,可实现DA转化。DA芯片用的是DAC8812,实现16位数模转化。-DA conversion, Verilog HDL code, the DA conversion can be achieved. DA-chip using a DAC8812, 16-bit analog-to achieve transformation.
FIFO
- 异步FIFO的实现,可综合,可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
verilog
- 一组练习,关于VHDL的一些基础的知识和练习可以参考一些具体的问题-A group of exercises, on a number of VHDL-based knowledge and practice can refer to some specific questions
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。 实验平台: 1. 一台PC机; 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
risc8
- PIC单片机的verilog实现,不记得在哪里下载的。源文件中应该有的。-PIC MCU Verilog realized, can not remember where to download. Source file should have.
dff
- 用vhdl编写的D触发器,锁存器等,不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
PLL
- 可以实现自动锁相环功能的C源程序代码模块,-Can be achieved automatically PLL function C source code modules,
100Examples
- verilog 语言 可以免费下载的程序-Verilog language can be downloaded for free procedures
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
display_control
- 一个LCD控制器的verilog源代码,可以方便的控制TFT LCD!-An LCD controller Verilog source code, can easily control TFT LCD!