搜索资源列表
i2cflash
- I2c的Verilog描述，可以读取at24c512存储器-I2c the Verilog descr iption can be read at24c512 memory
car
- 用VHDL实现的红外循迹小车程序，采用8个红外二极管（装在车头底部）识别路况，接L298电机驱动电路，能跑白色背景下的黑色赛道，且能应付道路分叉，孤岛及自启动等。-Implemented using VHDL infrared tracking car program, using eight infrared diodes (mounted on the front of the bottom) to identify traffic, then L298 motor driver circu
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
I2C
- 用verilog编写实现的I2C协议源码，自带控制台，解压后用ISE打开工程文件即可。-Prepared achieved with the I2C protocol verilog source code, comes with the console, after decompression project file can be opened with the ISE.
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
FPGA2SRAM
- verilog code that can implemented on ACEX1k FPGA for a SRAM-verilog code that can implemented on ACEX1k FPGA for a SRAM
yiweiDCTbianhuan
- 一维DCT变换的Verilog HDL源程序，在ISE中已经通过编译，可以参考里面的文档。-One-dimensional DCT transform Verilog HDL source code, in the ISE has been through the compilation, you can refer to inside the document.
m1_core.tar
- 一个小巧的mips处理器，verilog写的，大家可以-A small mips processor, verilog written, we can see
CPU
- verilog实现的一个简单的CPU，大家可下载去瞅瞅啊-verilog to achieve a simple CPU, you can download to Chou Chou ah
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
FPFA-DSP
- FPGA可以实现DSP算法，本材料提供了详细的实现方法，对原理与实现给出清晰的思路，是FPGA开发参考的好资料。-FPGA can implement DSP algorithms, this material provides a detailed implementation methods, theory and implementation gives a clear idea is a good reference information on FPGA development.
vga_module
- This source use to display a 256x256 RGB image from SRAM on a CRT monitor.You can use this to filter colors of the image.Image is loaded into SRAM by using DE2_control_panel
lcd16032
- 金鹏液晶LCD，OCMJ2X10C-2，4并口调用子程序，可直接移植-Jinpeng liquid crystal LCD, OCMJ2X10C-2, 4 parallel subroutine calls can be directly transplanted
CHICAGO5Manual
- 高科技的发展使芯片设计不再是半导体工业的领域，现场可编程逻辑阵列（FPGA）的出现使通过软件来快速实现芯片设计成为可能。本系统是广泛面向全球的工程技术人员和大专院校学生，使您能够在最短的时间内掌握FPGA的应用与VHDL/AHDL/Verilog HDL这一电子逻辑设计利器，迅速的加入高级电子设计人才行列。-The development of high-tech chip design is no longer the field of semiconductor industry, fiel
edaok_UART_FPGA
- 用FPGA实现UART的串口通信，可以设置数据位，校验位，奇偶校验等-With the FPGA to achieve UART serial communication, you can set the data bits, parity bit, parity, etc.
W5300_Driver_V1[1].1.1
- 硬件TCPIP协议栈芯片W5300的使用例子代码,该芯片内部通过硬件实现了TCPIP协议栈,可减少CPU运行协议栈的开销.-Hardware TCPIP protocol stack chips W5300 examples of the use of code, the chip hardware implementation of the internal adoption of the TCPIP protocol stack can reduce the CPU overhead of
fir
- Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
CANProtocolControllerIPCoreinVerilog
- 一种基于CAN协议的IP核源代码，用Verilog语言实现-CAN Protocol Controller IP Core in Verilog.
xge_mac
- 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below.