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booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to impr
the-design-of-16-bit-cpu
- 用vhdl硬件语言设计的16位cpu，上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
CPU
- 用VHDL编的简易16位和8位CPU，可完成加减乘法移位等功能，拥有源码和设计文档，资料齐全-Compiled with VHDL simple 16-bit and 8-bit CPU, to be completed by addition and subtraction multiplication shift functions, with source code and design documents, data and complete
计算机设计与实践实验 16位cpu设计
- 计算机设计与实践实验 16位cpu设计 使用用VHDL语言 -16-bit cpu design with VHDL
mips
- 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
CPU
- 用VHDL设计的cpu 用微指令方法设计 通过rom查表的方式进行设计-Cpu design with VHDL designed by microinstructions way through the design of look-up table rom
CPU
- 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
CPUVHDL
- CPU+VHDL代码及详细注释\一个老外写的 200多行代码-CPU+ VHDL code and detailed notes \ a foreigner wrote more than 200 lines of code
CPU
- 利用vhdl模拟实现CPU的功能，实现其中的加减乘除等多种运算-CPU utilization of vhdl simulation of the realization of the function, the realization of which, such as addition and subtraction, multiplication and division multiple computing
CPU
- Cpu with 8 bits in VHDL verilog Code
Exp6_SPI_AD_DA
- 用VHDL在SOPC试验箱中实现DA_AD转换，用ＶＨＤＬ硬件描述语言实现处理器CPU-With VHDL SOPC test box in DA_AD realization, with VHDL language processor CPU hardware descr iption
Digital.Logic.And.Microprocessor.Design.With.VHDL.
- 设计数字电路和CPU的教程，使用VHDL语言。国外牛人写的书，很强大，很详细，英文原版电子书。-Digital.Logic.And.Microprocessor.Design.With.VHDL
CPU-design
- 使用VHDL语言开发的CPU硬布线设计，在实验电路可以使用加法，和减法与或等简单操作-CPU using VHDL language development of hard-wired design, the circuit can be used in the experimental addition, and subtraction or other simple operations with
cpu
- 设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is c
POC_all
- poc即为cpu与外部设备，比如打印机的接口，用VHDL的编程来实现poc功能的仿真-poc is the cpu with an external device, such as the printer' s interface, programming with VHDL simulation capabilities to achieve poc
cpu
- 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
vhdl-pipeline-mips0
- MIPS CPU WITH PIPELINE procesador MIPS-FZA -- Autor: mahdi ahmadi -- Email: mahdi@fza.ir -- mahdifza@yahoo.com -- -- Version: 1.0
cpu
- 用vhdl实现了具有流水的cpu，实现30条基于mips指令的指令集-Achieved with vhdl cpu with water, to achieve 30 mips instruction based instruction set