搜索资源列表
DAC_TLV5616
- tlv5614的驱动程序,用verilog语言编写的,fpga芯片为altera公司的ep2c35。 调试成功放心使用-tlv5614 driver, using verilog language written in, fpga chips altera company ep2c35. Assured the success of the use of debugging
eda
- 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计,对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能,该系统无须外接D/A转换器及模拟比较器,结构简单,控制精度高,有广泛的应用前景。同时,控制系统中引入上位机控制功能,可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the desi
MyDDS
- 利用查找表法编写的DDS的verilog程序,节省了利用IP核实现需要的资源,软件为ISE,-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
dfefe.doc
- 该高频正弦信号发生器基于直接数字频率合成(DDS)和数字锁相环技术(DPLL),以微控制器(MCU)和现场可编程逻辑门阵列(FPGA)为核心,辅以必要的外围电路设计而成。系统主要由正弦信号发生、红外遥控、高速模数(A/D)-数模(D/A)转换、信号调制和后级处理等模块组成。-The high-frequency sinusoidal signal generator based on Direct Digital Synthesis (DDS) and digital PLL (DPLL), a
DFF
- actel fpga D触发器 verilog描述-pdf actel fpga d
D_latch
- actel fpga Verilog D锁存器-actel fpga Verilog D latch
8X8LED_verilog_fpga
- 8*8的LED 用VERILOG 写的FPGA,程序,这可是用在最近的项目中,下载用在最近的项目中,请标明出处!-8* 8 LED written with VERILOG FPGA, procedures, and this is used in a recent project, download used in recent projects, please credit!
file
- PAL-VGA格式转换器的设计,内部包含实现的FPGA代码-PAL-VGA format converter design, the internal code contains the implementation of the FPGA
The-FPGA-high-speed-data-acquisition
- 摘要:介绍了现场可编程门阵列FPGA(Field Programmable Gate Array)器件XCS30的主要特点、技 术参数、内部结构和工作原理,I}述了其在电力系统高速数据采集系统中的应用实例。电力数据采 集装置—馈线终端单元(FTU)需要监测多条线路的电压和电流,实时性要求高,充分利用FPGA 的并行处理能力,对输入信号实行同时采样、分时进行A/D转换,通过在FPGA片上构建的DRAM 进行数据的快速传输。FPGA在系统中承担了较多的实时任务,使DSP芯片TMS32
D
- FPGA VERILOG实现 D触发器 -FPGA VERILOG D flip-flop
delta-sigma-DAC
- 根据FPGA的∑-Δ D/A转换器的设计与实现策略,∑-Δ DAC的内部仅由2个10位的二进制加法器,1个10位的锁存器和一个D触发器组成,用FPGA实现时只需耗费极少的逻辑资源,即使用最小的FPGA也能实现。这是∑-Δ DAC实现的verilog语言-According to the FPGA Σ-Δ D/A converter design and implementation strategies, Σ-Δ DAC' s internal only by the two 10-bit
D-trigger
- FPGA/CPLD开发,基于VHDL语言的D触发器的实现-FPGA/CPLD development, based on VHDL implementation of the D flip-flop
D-trigger
- FPGA EPM1270 VHDL D触发器。完整文件夹包-FPGA EPM1270 VHDL D flip-flop. Complete document wallets
1-D-DWT_verilog-code
- Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The compu
about-the-experiment-of-FPGA
- FPGA相关实验程序包括点阵、A/D、D/A转换-Related experimental procedures include dot matrix FPGA, A/D, D/A converter
heartbeat
- 整个程序由心率传感器模块,体温传感器模块,3D计步器模块,FPGA开发板,A/D转换器,LCD显示屏等组成。(The entire program module by heart rate sensor, temperature sensor module, 3D pedometer module, FPGA development board, A/D converter, LCD display etc..)
fifo
- IL SAGIT D'UN FIFO EN DEscr iptION DE LANGUAGE vhdl
4.ADC_Ctrl
- 模数转换器即 A/D 转换器,或简称 ADC(Analog to Digital Conver),通常是指一个将 模拟信号转变为数字信号的电子元件。(Analog to digital converter, or A/D converter, or ADC. Analog signals are converted into digital signals.)
5.DAC
- 数模转换器即 D/A 转换器,或简称 DAC,是指将数字信号转变为模拟信号的电子元件。(A digital to analog converter, or D/A converter, or DAC, is an electronic component that converts digital signals into analog signals.)
FPGA
- ⑴实验要求基本要求: ①设置一个复位键,按下按键输出电压清零 ②设置两个功能键,控制输出电压以0.2V的步长进行加减。(Pin sets a reset button, press the button to output the voltage reset You set two function keys to control the output voltage by 0.2v step size.)