搜索资源列表
VHDL_AES_ZigBee
- 用VHDL实现的ZigBee模块控制算法以及AES加密算法，用于Xilinx的FPGA!-With the realization of VHDL ZigBee module control algorithm and AES encryption algorithms for Xilinx FPGA!
SSSSS
- 一种实用的基于FPGA的加密算法的设计，有AES和DES-A practical FPGA-based design of encryption algorithm, AES and DES have
1
- 一种基于FPGA的AES算法的低功耗实现,对于AES低功耗设计有帮助作用-FPGA-based AES algorithm to achieve low power consumption, low-power design for the AES helpful
fpga_code
- ZLG_EasyFPGA060开发板配套的源程序。包括：AES加密实验及文档，同步FIFO实验等项目。让新手快速掌握FPGA的开发流程，为进一步学习好FPGA打下坚实的基础。-ZLG_EasyFPGA060 development board supporting source. Include: AES encryption and document experiments, synchronous FIFO experiments and other projects. Novice to
AES
- Pipelined Implementation of AES Encryption Based on FPGA
aes_fsl_interface
- aes to fsl with xilinx fpga
dec_aes
- decription aes vhdl code for fpga
AES
- AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
20161227_sf
- AES加密算法中的列混合模块的FPGA实现源代码，采用Verillog语言，在软件Quartus II上综合-AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software
avs_aes_latest
- This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA
Coding Files
- We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
aes256
- 基于FPGA的AES256位加密，根据AES128位加密进行改编的，还存在一些问题需改善。(AES256 encryption based on FPGA,according to AES128 bit encryption.There are still some problems to be improved.)
AESj 加密解密Verilog
- 128位AES加密解密，可以在FPGA上实现