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基于verilog HDL语言的电子钟
- 基于verilog HDL语言的电子钟，多功能电子时钟,Verilog HDL language-based electronic bell, electronic multi-function clock
fpga_ads8364
- fpga控制ti的多通道高精度ad芯片ads8364的verilog源码-fpga multi-channel high-precision control ti ad-chip ads8364 the verilog source code
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
multiclock_design_guide
- 在FPGA设计中，多时钟设计策略。采用verilog描述。-In the FPGA design, multi-clock design strategy. Using Verilog descr iption.
clock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
clock
- 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
multi-functional_digital_clock
- 基于verilog的多功能数字钟，内含各功能模块-Verilog-based multi-functional digital clock that contains the function module
clock
- 实现多功能电子表，含有闹铃，时间精确到毫秒-Achieve multi-functional electronic watch, with alarm, time, milliseconds
multi-cycle-MIPS
- multicycle-MIPS verilog implementation
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
dianzibiao
- verilog语言编写的多功能电子表程序-verilog language, multi-function electronic spreadsheet programs
MIPS-multi-cycle-(Quarters-II--Verillig)
- Multi cycle MIPS processor verilog
Multi
- A Complete Multicycle CPU Written in Verilog Lang.
multi-CPU
- Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
Verilog-HDL-washer
- 智能洗衣机控制器 基于verilog hdl状态机 具有多种功能切换-Intelligent washing machine controller verilog hdl-based state machine has multi-functional switch
cpu-7-verilog
- 多周期cpu设计asadsdddasd-multi cpu design
kcsj
- 利用Verilog层次化设计的多功能数字时钟，可以调时，设置闹钟，仿广播台整点报时(The use of Verilog hierarchical design of multi-functional digital clock, you can set the alarm clock, similar to the broadcast station, the whole point of time)
FPGA_program
- 采用verilog实现RTLAB多路驱动程序(Using Verilog to achieve RTLAB multi-channel driver)
35_OV7725_VGA_DDR3_LX16_joint
- 多目摄像头同屏显示，实现图像分割，xilinx公司芯片，ISE平台开发(Multi camera on the same screen display, image segmentation, Xilinx company chip, ISE platform development)
multi
- 基于Verilog HDL 的乘法器，可以实现一些功能的计算(Multiplier based on Verilog HDL)