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靳远－源程序
- 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
leg_source
- verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
dsp_addmul
- DSP流水线算法，适用于对ＤＳＰ进行较深研究的人员使用-pipelined DSP algorithm that applies to the DSP for deeper study of the use of
fft_flp32_Complex
- 文件包为浮点快速傅立叶变换（32点）的汇编代码，运行在ADI的Visual DSP++平台上，由于结合了并行流水线指令，该算法具有很高的运行效率，可以被广泛使用在高速数字信号处理方面。-package for floating-point fast Fourier transform (32 points) compiled code, ADI operations in the Visual DSP platform, thanks to a combination of a parallel
pis
- Computer Architecture pipelined implementation simulator
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
lab4
- ics lab4 (csapp lab4) Software School, ICS, Autumn 2010 Optimizing the Performance of a Pipelined Processor-ics lab4 (csapp lab4) Software School, ICS, Autumn 2010 Optimizing the Performance of a Pipelined Processor
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
median-filter
- 基于FPGA的图像中值滤波算法的优化及实现vhdl-中值滤波 利用VHDL语言实现三级流水线中值滤波-FPGA-based image filtering algorithm optimization and realization of vhdl-median filter using VHDL language three pipelined median filter
fpga_FILTER
- 基于FPGA的可编程数字滤波器系统,基于FPGA的数字滤波器的设计与实现,基于FPGA流水线分布式算法的FIR滤波器的实现-FPGA-based programmable digital filter system, the digital filter based on FPGA Design and Implementation, Distributed Pipelined FPGA-based FIR filter algorithm to achieve
CORDIC
- ：CORDIC算法将复杂的算术运算转化为简单的加法和移位操作，然后逐次逼近结果。这种方法很好的兼顾了精度、速度和硬件复杂度，它与VLSI技术的结合对DSP算法的硬件实现具有极大的意义，因而在数字信号处理领域得到了广泛应用。本文首先简要介绍了CORDIC算法的原理，然后详细描述了双模式（旋转/向量）CORDIC算法的预处理和后处理，并且基于FPGA实现了流水线双模CORDIC算法。-By converting complex arithmetic into simple operations su
FPGA_common_idea
- 本文讨论的四种常用FPGA/CPLD 设计思想与技巧：乒乓操作、串并转换、流水线操作、数据接口同步化，都是FPGA/CPLD 逻辑设计的内在规律的体现，合理地采用这些设计思想能在FPGA/CPLD 设计工作种取得事半功倍的效果。-This article discusses the four commonly used FPGA/CPLD design ideas and techniques: ping-pong operation, strings, and conversion, pipe
mips_multi
- mips processor multicycle non-pipelined microprocessor by verilog
liushuixian_mul
- 流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
cordpipe
- pipelined cordic algorithm in hdl
ps2lab1
- pipelined CPU with hazards and forwarding unit
Pipelined-and-Parallel-Recursive-and-Adaptive-Fil
- Pipelined and Parallel IIR Recursive and Adaptive Filters design for hardware implementation
lesson6_pipelining
- Analysis of the MIPS 32-bit, pipelined processor using synthesized VHDL
pipelined
- mips processor pipelined